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authorHannah Williams <hannah.williams@intel.com>2016-06-08 17:39:37 -0700
committerMartin Roth <martinroth@google.com>2016-06-24 19:11:21 +0200
commit8ecd6f849c51bff6072f78e080b04a50735488b1 (patch)
tree58e015c646e7e763bece8b7ff46c21ac010876a3 /src/soc
parent82ef8ada82bd63ea7ce61843189fd4ee5de45cb5 (diff)
soc/intel/apollolake: Include _PTS, _WAK and _SWS
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15138 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/acpi/globalnvs.asl2
-rw-r--r--src/soc/intel/apollolake/acpi/platform.asl20
-rw-r--r--src/soc/intel/apollolake/include/soc/nvs.h14
3 files changed, 30 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 3597788421..b2b7f5306b 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -34,6 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PWRS, 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF
CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
+ PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
+ GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl
new file mode 100644
index 0000000000..f3202a0c48
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/platform.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2016 Intel Corp
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <soc/intel/common/acpi/platform.asl>
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index fda35561b0..c7918126d7 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -28,13 +28,15 @@
struct global_nvs_t {
/* Miscellaneous */
- uint8_t pcnt; /* 0x00 - Processor Count */
- uint8_t ppcm; /* 0x01 - Max PPC State */
- uint8_t lids; /* 0x02 - LID State */
- uint8_t pwrs; /* 0x03 - AC Power State */
- uint8_t dpte; /* 0x04 - Enable DPTF */
+ uint8_t pcnt; /* 0x00 - Processor Count */
+ uint8_t ppcm; /* 0x01 - Max PPC State */
+ uint8_t lids; /* 0x02 - LID State */
+ uint8_t pwrs; /* 0x03 - AC Power State */
+ uint8_t dpte; /* 0x04 - Enable DPTF */
uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
- uint8_t unused[247];
+ uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+ uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */
+ uint8_t unused[231];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;