diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-07-13 16:33:07 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-16 17:20:04 +0000 |
| commit | 79ab7d7780bfb0a23748afdd5b4832e23544b4df (patch) | |
| tree | 56af18119332c0dd9fa49e211d2017ca9b27186e /src/soc | |
| parent | d45835837985c4e97b55d09a42a2297da714d891 (diff) | |
soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatus
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390
No reason to have the firmware do it as well.
BUG=b:153001807, b:154756391
TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI
errors.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/acpi/pcie.asl | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index cb4be7fcaf..601de5247e 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -63,21 +63,3 @@ IUA2, 0x00000008, /* Index 0xF8: UART2 */ IUA3, 0x00000008, /* Index 0xF9: UART3 */ } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x60), /* AcpiPm1EvgBlk */ - P1EB, 16, - } - OperationRegion (P1E0, SystemIO, P1EB, 0x04) - Field (P1E0, ByteAcc, Nolock, Preserve) { - Offset(0x02), - , 14, - PEWD, 1, - } |