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authorAaron Durbin <adurbin@chromium.org>2014-11-06 15:17:33 -0600
committerPatrick Georgi <pgeorgi@google.com>2015-04-10 12:01:24 +0200
commit6cdacb37f0e84666831d78f4bf9af2cbc30cbb81 (patch)
tree00b24a90e82dabeabe6f02efacb513ca2da425de /src/soc
parent1f4db4046f911b2ed586509de5d8e109b46a9485 (diff)
arm64: secmon: add entry point for turned on CPUs
Newly turned on CPUs need a place to go bring its EL3 state inline with expectations. Plumb this path in for CPUs turning on as well as waking up from a power down state. Some of the infrastructure declarations were moved around for easier consumption in ramstage and secmon. Lastly, a psci_soc_init() is added to inform the SoC of the CPU's entry point as well do any initialization. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and booted. On entry point not actually utilized. Change-Id: I2af424c2906df159f78ed5e0a26a6bc0ba2ba24f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dbefec678a111e8b42acf2ae162c1ccdd7f9fd40 Original-Change-Id: I7b8c8c828ffb73752ca3ac1117cd895a5aa275d8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228296 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9422 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra132/psci.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/psci.c b/src/soc/nvidia/tegra132/psci.c
index b039dfbe6f..6ba39e09b5 100644
--- a/src/soc/nvidia/tegra132/psci.c
+++ b/src/soc/nvidia/tegra132/psci.c
@@ -19,6 +19,10 @@
#include <arch/psci.h>
+void psci_soc_init(uintptr_t cpu_on_entry)
+{
+}
+
static size_t children_at_level(int parent_level, uint64_t mpidr)
{
if (mpidr != 0)