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authorDuncan Laurie <dlaurie@google.com>2020-10-28 14:26:26 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-11-20 00:27:04 +0000
commit2b3de787a49e4a1ab0e47e9c6ce1115548ed3287 (patch)
tree29f8836b1eeb4d523eb0c604cc1587d28c4ec609 /src/soc
parent7f6a4845110cc74a97428b321627454e02c8d2fe (diff)
mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default
Set the default state of the TCSS PCIe RP0 to hidden so that coreboot does not allocate resources to this hotplug root port. The default behavior on the reference design is that there is only one USB4 port attached to port C1 while port C0 is only a USB3 port. Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and C1 ports, so these boards change the default to 'on' so that coreboot does allocate resources for the hotplug port. BUG=b:159143739 BRANCH=volteer TEST=build volteer and voxel and check the resulting static.c to ensure the device is hidden or not. Also boot with the two different configurations and ensure resources are assigned or not. Finally check that S0ix still functions with the C0 port set to 'hidden' after authorizing a PCIe tunnel on port C1. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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