diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-10 11:25:57 -0800 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 04:59:35 +0100 |
| commit | 006d73d2e224a06736e6a43b4109a3e70d344241 (patch) | |
| tree | 9f53195139e8f1fd4c55a125ace756df7ea4a613 /src/soc | |
| parent | c5f3685f4486a875c0957b713932e241c46ea537 (diff) | |
soc/intel/common: Wrap lines at 80 columns
Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18753
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/acpi/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/gma.h | 198 | ||||
| -rw-r--r-- | src/soc/intel/common/smihandler.c | 6 |
3 files changed, 110 insertions, 98 deletions
diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c index c27362473e..458b95fd54 100644 --- a/src/soc/intel/common/acpi/acpi.c +++ b/src/soc/intel/common/acpi/acpi.c @@ -71,8 +71,8 @@ __attribute__((weak)) uint32_t cpu_get_max_ratio(void) __attribute__((weak)) uint32_t cpu_get_bus_clock(void) { /* CPU bus clock is set by default here to 100MHz. - This function returns the bus clock in KHz. - */ + * This function returns the bus clock in KHz. + */ return 100 * KHz; } diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h index db09ca8698..3f943805fb 100644 --- a/src/soc/intel/common/gma.h +++ b/src/soc/intel/common/gma.h @@ -29,17 +29,17 @@ /* mailbox 0: header */ typedef struct { - u8 signature[16]; /* Offset 0 OpRegion signature */ - u32 size; /* Offset 16 OpRegion size */ - u32 version; /* Offset 20 OpRegion structure version */ - u8 sbios_version[32]; /* Offset 24 System BIOS build version */ - u8 vbios_version[16]; /* Offset 56 Video BIOS build version */ - u8 driver_version[16]; /* Offset 72 Graphic driver build version */ - u32 mailboxes; /* Offset 88 Mailboxes supported */ - u32 dmod; /* Offset 92 Driver Model */ - u32 pcon; /* Offset 96 Platform Capabilities */ - u16 dver[16]; /* Offset 100 GOP Version */ - u8 reserved[124]; /* Offset 132 Reserved */ + u8 signature[16]; /* Offset 0 OpRegion signature */ + u32 size; /* Offset 16 OpRegion size */ + u32 version; /* Offset 20 OpRegion structure version */ + u8 sbios_version[32]; /* Offset 24 System BIOS build version */ + u8 vbios_version[16]; /* Offset 56 Video BIOS build version */ + u8 driver_version[16]; /* Offset 72 Graphic drvr build version */ + u32 mailboxes; /* Offset 88 Mailboxes supported */ + u32 dmod; /* Offset 92 Driver Model */ + u32 pcon; /* Offset 96 Platform Capabilities */ + u16 dver[16]; /* Offset 100 GOP Version */ + u8 reserved[124]; /* Offset 132 Reserved */ } __attribute__((packed)) opregion_header_t; #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" @@ -59,100 +59,110 @@ typedef struct { /* mailbox 1: public ACPI methods */ typedef struct { - u32 drdy; /* Offset 0 Driver readiness */ - u32 csts; /* Offset 4 Status */ - u32 cevt; /* Offset 8 Current event */ + u32 drdy; /* Offset 0 Driver readiness */ + u32 csts; /* Offset 4 Status */ + u32 cevt; /* Offset 8 Current event */ u8 reserved[20]; /* Offset 12 Reserved */ - u32 didl; /* Offset 32 Supported display device 1 */ - u32 ddl2; /* Offset 36 Supported display device 2 */ - u32 ddl3; /* Offset 40 Supported display device 3 */ - u32 ddl4; /* Offset 44 Supported display device 4 */ - u32 ddl5; /* Offset 48 Supported display device 5 */ - u32 ddl6; /* Offset 52 Supported display device 6 */ - u32 ddl7; /* Offset 56 Supported display device 7 */ - u32 ddl8; /* Offset 60 Supported display device 8 */ - u32 cpdl; /* Offset 64 Currently present display device 1 */ - u32 cpl2; /* Offset 68 Currently present display device 2 */ - u32 cpl3; /* Offset 72 Currently present display device 3 */ - u32 cpl4; /* Offset 76 Currently present display device 4 */ - u32 cpl5; /* Offset 80 Currently present display device 5 */ - u32 cpl6; /* Offset 84 Currently present display device 6 */ - u32 cpl7; /* Offset 88 Currently present display device 7 */ - u32 cpl8; /* Offset 92 Currently present display device 8 */ - u32 cadl; /* Offset 96 Currently active display device 1 */ - u32 cal2; /* Offset 100 Currently active display device 2 */ - u32 cal3; /* Offset 104 Currently active display device 3 */ - u32 cal4; /* Offset 108 Currently active display device 4 */ - u32 cal5; /* Offset 112 Currently active display device 5 */ - u32 cal6; /* Offset 116 Currently active display device 6 */ - u32 cal7; /* Offset 120 Currently active display device 7 */ - u32 cal8; /* Offset 124 Currently active display device 8 */ - u32 nadl; /* Offset 128 Next active device 1 */ - u32 ndl2; /* Offset 132 Next active device 2 */ - u32 ndl3; /* Offset 136 Next active device 3 */ - u32 ndl4; /* Offset 140 Next active device 4 */ - u32 ndl5; /* Offset 144 Next active device 5 */ - u32 ndl6; /* Offset 148 Next active device 6 */ - u32 ndl7; /* Offset 152 Next active device 7 */ - u32 ndl8; /* Offset 156 Next active device 8 */ - u32 aslp; /* Offset 160 ASL sleep timeout */ - u32 tidx; /* Offset 164 Toggle table index */ - u32 chpd; /* Offset 168 Current hot plug enable indicator */ - u32 clid; /* Offset 172 Current lid state indicator */ - u32 cdck; /* Offset 176 Current docking state indicator */ - u32 sxsw; /* Offset 180 Display Switch notification on Sx State resume */ - u32 evts; /* Offset 184 Events supported by ASL */ - u32 cnot; /* Offset 188 Current OS Notification */ - u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */ - u32 ddl9; /* Offset 196 Extended Supported display device 1 */ - u32 dd10; /* Offset 200 Extended Supported display device 2 */ - u32 dd11; /* Offset 204 Extended Supported display device 3 */ - u32 dd12; /* Offset 208 Extended Supported display device 4 */ - u32 dd13; /* Offset 212 Extended Supported display device 5 */ - u32 dd14; /* Offset 216 Extended Supported display device 6 */ - u32 dd15; /* Offset 220 Extended Supported display device 7 */ - u32 cpl9; /* Offset 224 Extended Currently present device 1 */ - u32 cp10; /* Offset 228 Extended Currently present device 2 */ - u32 cp11; /* Offset 232 Extended Currently present device 3 */ - u32 cp12; /* Offset 236 Extended Currently present device 4 */ - u32 cp13; /* Offset 240 Extended Currently present device 5 */ - u32 cp14; /* Offset 244 Extended Currently present device 6 */ - u32 cp15; /* Offset 248 Extended Currently present device 7 */ + u32 didl; /* Offset 32 Supported display device 1 */ + u32 ddl2; /* Offset 36 Supported display device 2 */ + u32 ddl3; /* Offset 40 Supported display device 3 */ + u32 ddl4; /* Offset 44 Supported display device 4 */ + u32 ddl5; /* Offset 48 Supported display device 5 */ + u32 ddl6; /* Offset 52 Supported display device 6 */ + u32 ddl7; /* Offset 56 Supported display device 7 */ + u32 ddl8; /* Offset 60 Supported display device 8 */ + u32 cpdl; /* Offset 64 Currently present display device 1 */ + u32 cpl2; /* Offset 68 Currently present display device 2 */ + u32 cpl3; /* Offset 72 Currently present display device 3 */ + u32 cpl4; /* Offset 76 Currently present display device 4 */ + u32 cpl5; /* Offset 80 Currently present display device 5 */ + u32 cpl6; /* Offset 84 Currently present display device 6 */ + u32 cpl7; /* Offset 88 Currently present display device 7 */ + u32 cpl8; /* Offset 92 Currently present display device 8 */ + u32 cadl; /* Offset 96 Currently active display device 1 */ + u32 cal2; /* Offset 100 Currently active display device 2 */ + u32 cal3; /* Offset 104 Currently active display device 3 */ + u32 cal4; /* Offset 108 Currently active display device 4 */ + u32 cal5; /* Offset 112 Currently active display device 5 */ + u32 cal6; /* Offset 116 Currently active display device 6 */ + u32 cal7; /* Offset 120 Currently active display device 7 */ + u32 cal8; /* Offset 124 Currently active display device 8 */ + u32 nadl; /* Offset 128 Next active device 1 */ + u32 ndl2; /* Offset 132 Next active device 2 */ + u32 ndl3; /* Offset 136 Next active device 3 */ + u32 ndl4; /* Offset 140 Next active device 4 */ + u32 ndl5; /* Offset 144 Next active device 5 */ + u32 ndl6; /* Offset 148 Next active device 6 */ + u32 ndl7; /* Offset 152 Next active device 7 */ + u32 ndl8; /* Offset 156 Next active device 8 */ + u32 aslp; /* Offset 160 ASL sleep timeout */ + u32 tidx; /* Offset 164 Toggle table index */ + u32 chpd; /* Offset 168 Current hot plug enable indicator */ + u32 clid; /* Offset 172 Current lid state indicator */ + u32 cdck; /* Offset 176 Current docking state indicator */ + u32 sxsw; /* Offset 180 Display Switch notification on Sx State + * resume + */ + u32 evts; /* Offset 184 Events supported by ASL */ + u32 cnot; /* Offset 188 Current OS Notification */ + u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */ + u32 ddl9; /* Offset 196 Extended Supported display device 1 */ + u32 dd10; /* Offset 200 Extended Supported display device 2 */ + u32 dd11; /* Offset 204 Extended Supported display device 3 */ + u32 dd12; /* Offset 208 Extended Supported display device 4 */ + u32 dd13; /* Offset 212 Extended Supported display device 5 */ + u32 dd14; /* Offset 216 Extended Supported display device 6 */ + u32 dd15; /* Offset 220 Extended Supported display device 7 */ + u32 cpl9; /* Offset 224 Extended Currently present device 1 */ + u32 cp10; /* Offset 228 Extended Currently present device 2 */ + u32 cp11; /* Offset 232 Extended Currently present device 3 */ + u32 cp12; /* Offset 236 Extended Currently present device 4 */ + u32 cp13; /* Offset 240 Extended Currently present device 5 */ + u32 cp14; /* Offset 244 Extended Currently present device 6 */ + u32 cp15; /* Offset 248 Extended Currently present device 7 */ u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */ } __attribute__((packed)) opregion_mailbox1_t; /* mailbox 2: software sci interface */ typedef struct { - u32 scic; /* Offset 0 Software SCI function number parameters */ - u32 parm; /* Offset 0 Software SCI function number parameters */ - u32 dslp; /* Offset 8 Driver sleep timeout */ + u32 scic; /* Offset 0 Software SCI function number parameters */ + u32 parm; /* Offset 4 Software SCI function number parameters */ + u32 dslp; /* Offset 8 Driver sleep timeout */ u8 reserved[244]; /* Offset 12 Reserved */ } __attribute__((packed)) opregion_mailbox2_t; /* mailbox 3: power conservation */ typedef struct { - u32 ardy; /* Offset 0 Driver readiness */ - u32 aslc; /* Offset 4 ASLE interrupt command / status */ - u32 tche; /* Offset 8 Technology enabled indicator */ - u32 alsi; /* Offset 12 Current ALS illuminance reading */ - u32 bclp; /* Offset 16 Backlight britness to set */ - u32 pfit; /* Offset 20 Panel fitting Request */ - u32 cblv; /* Offset 24 Brightness Current State */ - u16 bclm[20]; /* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */ - u32 cpfm; /* Offset 68 Panel Fitting Current Mode */ - u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */ - u8 plut[74]; /* Offset 76 Panel Look Up Table */ - u32 pfmb; /* Offset 150 PWM Frequency and Minimum Brightness */ - u32 ccdv; /* Offset 154 Color Correction Default Values */ - u32 pcft; /* Offset 158 Power Conservation Features */ - u32 srot; /* Offset 162 Supported Rotation angle */ - u32 iuer; /* Offset 166 Intel Ultrabook Event Register */ - u64 fdsp; /* Offset 170 FFS Display Physical address */ - u32 fdss; /* Offset 178 FFS Display Size */ - u32 stat; /* Offset 182 State Indicator */ - u64 rvda; /* Offset 186 (Igd opregion offset 0x3BAh) Physical address of Raw VBT data */ - u32 rvds; /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */ - u8 reserved[58]; /* Offset 198 Reserved */ + u32 ardy; /* Offset 0 Driver readiness */ + u32 aslc; /* Offset 4 ASLE interrupt command / status */ + u32 tche; /* Offset 8 Technology enabled indicator */ + u32 alsi; /* Offset 12 Current ALS illuminance reading */ + u32 bclp; /* Offset 16 Backlight britness to set */ + u32 pfit; /* Offset 20 Panel fitting Request */ + u32 cblv; /* Offset 24 Brightness Current State */ + u16 bclm[20]; /* Offset 28 Backlight Brightness Level Duty + * Cycle Mapping Table + */ + u32 cpfm; /* Offset 68 Panel Fitting Current Mode */ + u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */ + u8 plut[74]; /* Offset 76 Panel Look Up Table */ + u32 pfmb; /* Offset 150 PWM Frequency and Minimum + * Brightness + */ + u32 ccdv; /* Offset 154 Color Correction Default Values */ + u32 pcft; /* Offset 158 Power Conservation Features */ + u32 srot; /* Offset 162 Supported Rotation angle */ + u32 iuer; /* Offset 166 Intel Ultrabook Event Register */ + u64 fdsp; /* Offset 170 FFS Display Physical address */ + u32 fdss; /* Offset 178 FFS Display Size */ + u32 stat; /* Offset 182 State Indicator */ + u64 rvda; /* Offset 186 (Igd opregion offset 0x3BAh) + * Physical address of Raw VBT data + */ + u32 rvds; /* Offset 194 (Igd opregion offset 0x3C2h) + * Size of Raw VBT data + */ + u8 reserved[58]; /* Offset 198 Reserved */ } __attribute__((packed)) opregion_mailbox3_t; #define IGD_BACKLIGHT_BRIGHTNESS 0xff diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/smihandler.c index da91c4516c..549a914813 100644 --- a/src/soc/intel/common/smihandler.c +++ b/src/soc/intel/common/smihandler.c @@ -407,7 +407,8 @@ static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg) return value; } -static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, uint64_t val) +static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, + uint64_t val) { em64t100_smm_state_save_area_t *smm_state = state; switch (reg) { @@ -458,7 +459,8 @@ static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg) return value; } -static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, uint64_t val) +static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, + uint64_t val) { em64t101_smm_state_save_area_t *smm_state = state; switch (reg) { |