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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-01-29 18:08:16 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-07 16:24:55 +0000 |
| commit | f3c57a7c28a3c66d2ade3e2b3108fd58b60c2a7c (patch) | |
| tree | 61525ac36d3d5044860b7e18f2b48b9ea9d32e67 /src/soc/ucb | |
| parent | 8d6e0e0a72ed81d44ba61add0c2aab55bb217412 (diff) | |
amd/stoneyridge: Put stage cache into TSEG
Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem. Increase the size
reserved in TSEG.
Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/ucb')
0 files changed, 0 insertions, 0 deletions