diff options
author | Ronald G. Minnich <rminnich@gmail.com> | 2014-11-26 19:25:47 +0000 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2014-12-01 19:06:43 +0100 |
commit | e0e784a456c4d64e5e88ce578371fe6c538db559 (patch) | |
tree | 7557a07ab68659eaf81ac50fc860a288055e0845 /src/soc/ucb | |
parent | 796fe068d3c47f873b82c65cc0591f88f87b0a85 (diff) |
Add UCB RISCV support for architecture, soc, and emulation mainboard..
Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/ucb')
-rw-r--r-- | src/soc/ucb/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/ucb/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/ucb/riscv/Kconfig | 11 | ||||
-rw-r--r-- | src/soc/ucb/riscv/Makefile.inc | 3 | ||||
-rw-r--r-- | src/soc/ucb/riscv/cbmem.c | 24 |
5 files changed, 40 insertions, 0 deletions
diff --git a/src/soc/ucb/Kconfig b/src/soc/ucb/Kconfig new file mode 100644 index 0000000000..7af50cb87a --- /dev/null +++ b/src/soc/ucb/Kconfig @@ -0,0 +1 @@ +source src/soc/ucb/riscv/Kconfig diff --git a/src/soc/ucb/Makefile.inc b/src/soc/ucb/Makefile.inc new file mode 100644 index 0000000000..35bc72871c --- /dev/null +++ b/src/soc/ucb/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_UCB_RISCV) += riscv diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig new file mode 100644 index 0000000000..d1e4ba7560 --- /dev/null +++ b/src/soc/ucb/riscv/Kconfig @@ -0,0 +1,11 @@ +config SOC_UCB_RISCV + select ARCH_RISCV + select ARCH_BOOTBLOCK_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + bool + default n + +if SOC_UCB_RISCV + +endif diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc new file mode 100644 index 0000000000..c25a2fccdb --- /dev/null +++ b/src/soc/ucb/riscv/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += cbmem.c + +ramstage-y += cbmem.c diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c new file mode 100644 index 0000000000..9c3ee989a6 --- /dev/null +++ b/src/soc/ucb/riscv/cbmem.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + // TODO: find out how RISCV stores this. + return (void *)0x1fff000; +} |