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| author | Ronald G. Minnich <rminnich@gmail.com> | 2018-12-19 17:52:43 -0800 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2019-01-17 04:59:09 +0000 |
| commit | 05358047290b5e60cf3c0dc7e967267a03d5c4ce (patch) | |
| tree | ed4340b82c8fa9ae78bf7b8095aa1ad952ef8202 /src/soc/ucb | |
| parent | cc394d4d37533a4977c1da629c8ebf405a91d32a (diff) | |
riscv: create Kconfig architecture features for new parts
RISCV parts can be created with any one of four CPU modes enabled,
with or without PMP, and with either 32 or 64 bit XLEN.
In anticipation of parts to come, create the Kconfig variables for these
architecture attributes.
Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30348
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/ucb')
| -rw-r--r-- | src/soc/ucb/riscv/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index 638d7345c2..5a43aa63c6 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,5 +1,9 @@ config SOC_UCB_RISCV select ARCH_RISCV + select ARCH_RISCV_RV64 + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP select ARCH_BOOTBLOCK_RISCV select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV |