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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-08-11 22:49:14 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2016-08-15 18:24:42 +0200 |
| commit | 28a3ee6d29738866594721c6dfc9ac25a9ef23d8 (patch) | |
| tree | 8cc9cd250598151a630d71a9f4deb2a964452f64 /src/soc/ucb | |
| parent | 12974436a98615c93c0489c88249e9fad2897438 (diff) | |
soc/ucb/riscv: select BOOTBLOCK_CONSOLE
Change-Id: I847d7686dec04e9fae7db13d53adc8ca32c56f3a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/ucb')
| -rw-r--r-- | src/soc/ucb/riscv/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index 744edffa1b..ff50f6f835 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -4,6 +4,7 @@ config SOC_UCB_RISCV select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV + select BOOTBLOCK_CONSOLE bool default n |