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| author | vbpandya <pandyavarshit@gmail.com> | 2023-09-22 20:49:37 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-28 13:37:56 +0000 |
| commit | 87d8b8cff0ec36b0cd2a596d1639a90756d91882 (patch) | |
| tree | 4882d833ed5ec06833c2c30df2541c25c2acf945 /src/soc/ucb/riscv | |
| parent | f1bf2d919044902d60b1a36eba16feba4a6c8b3d (diff) | |
soc/amd/genoa: Add chipset.cb
Change-Id: I6c9879a9f06f81d577bc09f6001158d7f9326362
Signed-off-by: vbpandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78082
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions