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| author | Jian Tong <tongjian@huaqin.corp-partner.google.com> | 2024-08-15 14:28:27 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-02 03:36:48 +0000 |
| commit | 6f07ca947138d136339f0638ee03556be56e0181 (patch) | |
| tree | cd693e9b1f8f886fe77aad470698d22488aa528e /src/soc/ucb/riscv | |
| parent | 35ac087630d9355992c5355edb69ca6783d6fd97 (diff) | |
mb/google/brox/var/lotso: Update verb table
Update verb table provided by Realtek on 20240710.
Restults: SNR > 90 (spec>=90).
BUG=b:349996984
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: Ic4f03d09010efa7e32713b2697d5832255f64317
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83920
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions