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| author | Jincheng Li <jincheng.li@intel.com> | 2024-09-12 20:20:55 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-09-23 08:37:40 +0000 |
| commit | e8bff7c010573643204b8a8112439cfa6dc3dffc (patch) | |
| tree | 3663191d7652d14c4b311389024f7f81606f3eba /src/soc/ucb/riscv | |
| parent | 7f7728decdb408539c10249ace40f52197a857f7 (diff) | |
Documentation/soc/intel/xeon_sp: Update Xeon 6 test config
Change-Id: Ia54af1495a0146be3e5c3e74a0dcfef6785d6371
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84331
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions