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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-08-31 10:40:29 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-14 14:04:30 +0000 |
| commit | 89356d142bc4678e8aa030b298faa42396f20795 (patch) | |
| tree | 54c632b22a43285960664395d2469aa71960145d /src/soc/ucb/riscv | |
| parent | 48e7d4902008eb5b9fd8ea793c88b2f8a1135c69 (diff) | |
mb/intel/adlrvp_p: Enable TCSS USB ports device path
TEST=Boot RVP, ensure Type C ports operate correctly.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Iadc0df2e6e29a5afbcbb7db1ae0be6546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions