diff options
author | Usha P <usha.p@intel.com> | 2022-03-18 10:10:17 +0530 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-21 13:06:24 +0000 |
commit | 86f4352a47a15fe69a0ea2b3a2a455ef863e7917 (patch) | |
tree | b41247b0cc28e657fcae386f5c238f5df6224386 /src/soc/ucb/riscv | |
parent | 28315f82040339c94941e17fcbe64c939e3a5994 (diff) |
mb/intel/adlrvp: Set half_populated true for ADL-N
Alder Lake-N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.
Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.
BRANCH=NONE
TEST=Build and boot ADL-N RVP.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62913
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions