diff options
| author | Tyler Wang <tyler.wang@quanta.corp-partner.google.com> | 2021-09-13 15:18:13 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-14 23:19:01 +0000 |
| commit | 4095291808b04544346432ca675e6fbfbb7ed11c (patch) | |
| tree | b3455095a1f9bb8cfa6dd494872a0489f63ce23d /src/soc/ucb/riscv | |
| parent | 89356d142bc4678e8aa030b298faa42396f20795 (diff) | |
src/soc/intel/jasperlake/spd: Update SPDs
Due to CL:55000 modified MT53E1G32D2NP-046 WT:B settings
and CL:56597 add new memory in global_lp4x_mem_parts.json.txt,
update SPDs using gen_spd.go for JSL:
Modify:
1.MT53E1G32D2NP-046 WT:B(lp4x-spd-5.hex --> lp4x-spd-3.hex)
Add:
1.H54G46CYRBX267,lp4x-spd-1.hex
2.H54G56CYRBX247,lp4x-spd-3.hex
3.K4U6E3S4AB-MGCL,lp4x-spd-1.hex
4.K4UBE3D4AB-MGCL,lp4x-spd-3.hex
BUG=b:199032134
TEST=emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I45b9275403fc4166fc56ae4c368c7a222141e150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions