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| author | Philipp Hug <philipp@hug.cx> | 2018-09-13 22:10:06 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-14 09:27:29 +0000 |
| commit | 31dbfbc405ba7b26cacd2cfcaeff95e52d60ad99 (patch) | |
| tree | cdb6289d6ef7220b13772d4b6b404fd2f17dde9e /src/soc/ucb/riscv | |
| parent | 688eec1b97c66e308e4a77a74d979da4ff20e13b (diff) | |
soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization
Add original files from SiFive bootloader.
Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions