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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-04 14:12:01 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-10 22:40:59 +0000 |
| commit | 2abbe467658a8e4479c381330e85e126c8f42a90 (patch) | |
| tree | 814bb1a711c25c03e9b502520336bfdd98cad2df /src/soc/ucb/riscv | |
| parent | 1d4bdda47f030d01418936d3399856dddfa7f43b (diff) | |
soc/intel/broadwell: Use common SB RTC code
Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions