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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-04-19 15:18:02 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-04 23:44:33 +0200 |
| commit | 062ef1cca6c1cd70828288181129ba0d0addd4ab (patch) | |
| tree | fd14ded78fb9ebfd443f7fdce32bf7c6ee61bd37 /src/soc/ucb/riscv | |
| parent | a03609b49600f05ec37e1796676954a3dc14faa3 (diff) | |
AGESA boards: Split dispatcher to romstage and ramstage
The way dispatcher table is set up prevents linker from
optimizing unused code away, we currently have raminit in ramstage.
Optimize this manually by configuring AGESA_ENTRY booleans for
romstage and ramstage separately. This will remove references in
FuncParamsInfo and DispatchTable -arrays.
All boards now include multi-core dispatcher, it has minimal footprint:
AGESA_ENTRY_LATE_RUN_AP_TASK
ACPI S3 support depends on HAVE_ACPI_RESUME being enabled:
AGESA_ENTRY_INIT_RESUME
AGESA_ENTRY_INIT_LATE_RESTORE
AGESA_ENTRY_INIT_S3SAVE
Disabled for all boards as it was not used:
AGESA_ENTRY_INIT_GENERAL_SERVICES
Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14417
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions