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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-17 15:36:45 +0200 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-11-09 16:02:19 +0000 |
| commit | b48caadad54196245f0e7dfcb92caa21e7112307 (patch) | |
| tree | 7652c60718b3eac5f008fba0a8fee34511aa8560 /src/soc/ucb/riscv/chip.c | |
| parent | cc66b56c80862a59117a4582abc8d59f092ac59c (diff) | |
soc/intel: generate SSDT instead of using GNVS for SGX
GNVS should not be used for values that are static at runtime. Thus,
use SSDT for the SGX fields.
Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/ucb/riscv/chip.c')
0 files changed, 0 insertions, 0 deletions