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| author | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-06-06 10:58:33 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 22:01:26 +0000 |
| commit | 2813c7c10c54e176ea0cd5413a8eb78f1664a1c9 (patch) | |
| tree | 12860cebb1048bf1c15305191d71ff4afbfec044 /src/soc/ucb/riscv/cbmem.c | |
| parent | ea66c9899b024e896dd810b7b99cff2a00b78f9d (diff) | |
mb/google/myst: Correct CROS_WP_GPIO to active high
HW has invert the signal, set it to active high.
BUG=b:285964562
TEST=check crossystem wpsw_cur change as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75628
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/ucb/riscv/cbmem.c')
0 files changed, 0 insertions, 0 deletions