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| author | Ronald G. Minnich <rminnich@gmail.com> | 2014-11-26 19:25:47 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2014-12-01 19:06:43 +0100 |
| commit | e0e784a456c4d64e5e88ce578371fe6c538db559 (patch) | |
| tree | 7557a07ab68659eaf81ac50fc860a288055e0845 /src/soc/ucb/riscv/Kconfig | |
| parent | 796fe068d3c47f873b82c65cc0591f88f87b0a85 (diff) | |
Add UCB RISCV support for architecture, soc, and emulation mainboard..
Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/ucb/riscv/Kconfig')
| -rw-r--r-- | src/soc/ucb/riscv/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig new file mode 100644 index 0000000000..d1e4ba7560 --- /dev/null +++ b/src/soc/ucb/riscv/Kconfig @@ -0,0 +1,11 @@ +config SOC_UCB_RISCV + select ARCH_RISCV + select ARCH_BOOTBLOCK_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + bool + default n + +if SOC_UCB_RISCV + +endif |