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authorSam Lewis <sam.vr.lewis@gmail.com>2020-08-06 21:13:22 +1000
committerArthur Heymans <arthur@aheymans.xyz>2021-03-30 11:21:49 +0000
commit7cbf391bce785cf3a815dc6a841f80611b4db6fe (patch)
treed481ad50ffedbbccc7e051c092849cb760509d9c /src/soc/ti
parent1d8d99bfd93602bbcc4f318f384a93cdad045705 (diff)
mb/ti/beaglebone: Initialize DDR3
Adds initialisation of 512MB of DDR memory on the BBB to the romstage. The parameters for the DDR peripherals are taken from U-Boot. TEST: Booted from romstage into ramstage. Also successfully managed to run the "ram_check" in lib.h. Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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