riscv: add support smp_pause / smp_resume

See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.

Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>

4 files changed, 11 insertions, 27 deletions

diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index bee8292199..72305d67a9 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -39,4 +39,12 @@ config RISCV_CODEMODEL
 	string
 	default "medany"
 
+config RISCV_HART_NUM
+	int
+	default 5
+
+config RISCV_WORKING_HARTID
+	int
+	default 0
+
 endif
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
index e2bdd03a00..fef859d9e4 100644
--- a/src/soc/sifive/fu540/Makefile.inc
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -19,6 +19,7 @@ bootblock-y += media.c
 bootblock-y += bootblock.c
 
 romstage-y += uart.c
+romstage-y += clint.c
 romstage-y += media.c
 romstage-y += sdram.c
 romstage-y += cbmem.c
diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c
index 00aec1ab37..fb4b97fbb3 100644
--- a/src/soc/sifive/fu540/clint.c
+++ b/src/soc/sifive/fu540/clint.c
@@ -14,9 +14,9 @@
  */
 
 #include <mcall.h>
+#include <stdint.h>
 #include <arch/io.h>
 #include <soc/addressmap.h>
-#include <soc/clint.h>
 
 void mtime_init(void)
 {
@@ -27,6 +27,5 @@ void mtime_init(void)
 
 void set_msip(int hartid, int val)
 {
-	long hart_id = read_csr(mhartid);
-	write32((void *)(FU540_CLINT + 4 * hart_id), !!val);
+	write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val);
 }
diff --git a/src/soc/sifive/fu540/include/soc/clint.h b/src/soc/sifive/fu540/include/soc/clint.h
deleted file mode 100644
index d2399c220a..0000000000
--- a/src/soc/sifive/fu540/include/soc/clint.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 HardenedLinux
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_SIFIVE_FU540_CLINT_H
-#define __SOC_SIFIVE_FU540_CLINT_H
-
-/* This function is used to set MSIP.
- * It can be used to send an IPI (inter-processor interrupt) to
- * another hart*/
-void set_msip(int hartid, int val);
-
-#endif