diff options
| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2019-04-24 10:19:07 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-29 12:18:54 +0000 |
| commit | f81c589ad25580b82a0c61031168385e8057293d (patch) | |
| tree | eb21d7e9a89847466874bd5b5d9344613160152e /src/soc/sifive | |
| parent | 3391a31cf9e74fc9e40d876aa6689e98af38882d (diff) | |
soc/intel/apollolake/bootblock: Clear the GPI IS & IE registers
Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.
BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/sifive')
0 files changed, 0 insertions, 0 deletions