src/sifive: Add the SiFive Freedom Unleashed 540 SoC

The FU540 is the first RISC-V SoC with the necessary resources to run
Linux (an external memory interface, MMU, etc).

More information is available on SiFive's website:
https://www.sifive.com/products/hifive-unleashed/

Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

9 files changed, 226 insertions, 0 deletions

diff --git a/src/soc/sifive/Kconfig b/src/soc/sifive/Kconfig
new file mode 100644
index 0000000000..14900be4ba
--- /dev/null
+++ b/src/soc/sifive/Kconfig
@@ -0,0 +1,2 @@
+# Load all chipsets
+source "src/soc/sifive/*/Kconfig"
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
new file mode 100644
index 0000000000..d247c280b5
--- /dev/null
+++ b/src/soc/sifive/fu540/Kconfig
@@ -0,0 +1,26 @@
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2018 Jonathan Neuschäfer
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+config SOC_SIFIVE_FU540
+	bool
+	select ARCH_RISCV
+	select ARCH_BOOTBLOCK_RISCV
+	select ARCH_VERSTAGE_RISCV
+	select ARCH_ROMSTAGE_RISCV
+	select ARCH_RAMSTAGE_RISCV
+	select BOOTBLOCK_CONSOLE
+	select DRIVERS_UART_SIFIVE
+
+if SOC_SIFIVE_FU540
+
+endif
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
new file mode 100644
index 0000000000..8a2f3a692b
--- /dev/null
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -0,0 +1,33 @@
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2018 Jonathan Neuschäfer
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+ifeq ($(CONFIG_SOC_SIFIVE_FU540),y)
+
+bootblock-y += uart.c
+bootblock-y += media.c
+bootblock-y += bootblock.c
+
+romstage-y += uart.c
+romstage-y += media.c
+
+ramstage-y += uart.c
+ramstage-y += media.c
+ramstage-y += cbmem.c
+
+CPPFLAGS_common += -Isrc/soc/sifive/fu540/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	@printf "    GPT        $(notdir $(@))\n"
+	@util/riscv/sifive-gpt.py $< $@
+
+endif
diff --git a/src/soc/sifive/fu540/bootblock.c b/src/soc/sifive/fu540/bootblock.c
new file mode 100644
index 0000000000..203081c90c
--- /dev/null
+++ b/src/soc/sifive/fu540/bootblock.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/addressmap.h>
+
+void bootblock_soc_init(void)
+{
+	printk(BIOS_INFO, "Boot mode: %d\n", read32((uint32_t *)FU540_MSEL));
+}
diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c
new file mode 100644
index 0000000000..8648370f20
--- /dev/null
+++ b/src/soc/sifive/fu540/cbmem.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+	/* dummy value */
+	return (void *)(4ULL * GiB);
+}
diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h
new file mode 100644
index 0000000000..904c8b6589
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/addressmap.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define FU540_MSEL		0x00001000
+#define FU540_DTIM		0x01000000
+#define FU540_L2LIM		0x08000000
+#define FU540_UART0		0x10010000
+#define FU540_UART(x)		(FU540_UART0 + 0x1000 * (x))
+#define FU540_PRCI		0x10000000
+#define FU540_QSPI0		0x10040000
+#define FU540_QSPI1		0x10041000
+#define FU540_QSPI2		0x10050000
+#define FU540_GPIO		0x10060000
+#define FU540_OTP		0x10070000
+#define FU540_PINCTRL		0x10080000
+#define FU540_ETHMAC		0x10090000
+#define FU540_ETHMGMT		0x100a0000
+#define FU540_DDRCTRL		0x100b0000
+#define FU540_DDRMGMT		0x100c0000
+#define FU540_QSPI0FLASH	0x20000000
+#define FU540_QSPI1FLASH	0x30000000
+#define FU540_DRAM		0x80000000
diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld
new file mode 100644
index 0000000000..a03c03d345
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/memlayout.ld
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <soc/addressmap.h>
+
+#include <arch/header.ld>
+
+#define L2LIM_START(addr) SYMBOL(l2lim, addr)
+#define L2LIM_END(addr) SYMBOL(el2lim, addr)
+
+SECTIONS
+{
+	L2LIM_START(FU540_L2LIM)
+	BOOTBLOCK(FU540_L2LIM, 64K)
+	STACK(FU540_L2LIM + 64K, 4K)
+	PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K)
+	ROMSTAGE(FU540_L2LIM + 128K, 128K)
+	L2LIM_END(FU540_L2LIM + 2M)
+
+	DRAM_START(FU540_DRAM)
+	RAMSTAGE(FU540_DRAM, 256K)
+}
diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c
new file mode 100644
index 0000000000..7b9ccb0e3c
--- /dev/null
+++ b/src/soc/sifive/fu540/media.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot_device.h>
+
+/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */
+static struct mem_region_device mdev =
+	MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+	return &mdev.rdev;
+}
diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c
new file mode 100644
index 0000000000..940dc97856
--- /dev/null
+++ b/src/soc/sifive/fu540/uart.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+#include <soc/addressmap.h>
+
+uintptr_t uart_platform_base(int idx)
+{
+	if (idx < 2)
+		return FU540_UART(idx);
+	else
+		return 0;
+}