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authorXiang Wang <wxjstz@126.com>2018-07-19 17:09:12 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-07-30 19:02:13 +0000
commite8d0c0092a71c5890a1dfbdc7b941dc5e05b0501 (patch)
tree29d10897bcdd24217af4fd84b3d610a192e3bf27 /src/soc/sifive
parentdbf5a5d0f8c63269a8f4fed72b70fbcc3d52e161 (diff)
riscv: delete src/arch/riscv/prologue.inc
This code was copied from x86. It is not needed for RISC-V. Change-Id: If6c3bfdc4090e45d171e68a28d27c38dabe91687 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27544 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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