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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-04 01:59:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-12-05 09:44:23 +0000 |
| commit | 455d7b74abdcc05ead46e1b4ca0f969df4f9a025 (patch) | |
| tree | 6f4a1b3fe8d4a5105d13f968e3f9f1b7c96d4761 /src/soc/sifive | |
| parent | c6ef514e93734baafb5e613982dc3b249497960e (diff) | |
soc/amd/picasso/tsc: fix clock divisor range check
The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.
TEST=Compared with Picasso's PPR #55570
Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/sifive')
0 files changed, 0 insertions, 0 deletions