riscv: add support smp_pause / smp_resume

See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.

Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>

1 files changed, 0 insertions, 24 deletions

diff --git a/src/soc/sifive/fu540/include/soc/clint.h b/src/soc/sifive/fu540/include/soc/clint.h
deleted file mode 100644
index d2399c220a..0000000000
--- a/src/soc/sifive/fu540/include/soc/clint.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 HardenedLinux
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_SIFIVE_FU540_CLINT_H
-#define __SOC_SIFIVE_FU540_CLINT_H
-
-/* This function is used to set MSIP.
- * It can be used to send an IPI (inter-processor interrupt) to
- * another hart*/
-void set_msip(int hartid, int val);
-
-#endif