riscv: add support smp_pause / smp_resume

See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.

Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>

1 files changed, 2 insertions, 3 deletions

diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c
index 00aec1ab37..fb4b97fbb3 100644
--- a/src/soc/sifive/fu540/clint.c
+++ b/src/soc/sifive/fu540/clint.c
@@ -14,9 +14,9 @@
  */
 
 #include <mcall.h>
+#include <stdint.h>
 #include <arch/io.h>
 #include <soc/addressmap.h>
-#include <soc/clint.h>
 
 void mtime_init(void)
 {
@@ -27,6 +27,5 @@ void mtime_init(void)
 
 void set_msip(int hartid, int val)
 {
-	long hart_id = read_csr(mhartid);
-	write32((void *)(FU540_CLINT + 4 * hart_id), !!val);
+	write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val);
 }