src/sifive: Add the SiFive Freedom Unleashed 540 SoC

The FU540 is the first RISC-V SoC with the necessary resources to run
Linux (an external memory interface, MMU, etc).

More information is available on SiFive's website:
https://www.sifive.com/products/hifive-unleashed/

Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 33 insertions, 0 deletions

diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
new file mode 100644
index 0000000000..8a2f3a692b
--- /dev/null
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -0,0 +1,33 @@
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2018 Jonathan Neuschäfer
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+ifeq ($(CONFIG_SOC_SIFIVE_FU540),y)
+
+bootblock-y += uart.c
+bootblock-y += media.c
+bootblock-y += bootblock.c
+
+romstage-y += uart.c
+romstage-y += media.c
+
+ramstage-y += uart.c
+ramstage-y += media.c
+ramstage-y += cbmem.c
+
+CPPFLAGS_common += -Isrc/soc/sifive/fu540/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	@printf "    GPT        $(notdir $(@))\n"
+	@util/riscv/sifive-gpt.py $< $@
+
+endif