arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

32 files changed, 825 insertions, 896 deletions

diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c
index 0986f8b9bd..89001ecf14 100644
--- a/src/soc/samsung/exynos5250/clock.c
+++ b/src/soc/samsung/exynos5250/clock.c
@@ -178,21 +178,21 @@ unsigned long get_pll_clk(int pllreg)
 
 	switch (pllreg) {
 	case APLL:
-		r = readl(&exynos_clock->apll_con0);
+		r = read32(&exynos_clock->apll_con0);
 		break;
 	case BPLL:
-		r = readl(&exynos_clock->bpll_con0);
+		r = read32(&exynos_clock->bpll_con0);
 		break;
 	case MPLL:
-		r = readl(&exynos_clock->mpll_con0);
+		r = read32(&exynos_clock->mpll_con0);
 		break;
 	case EPLL:
-		r = readl(&exynos_clock->epll_con0);
-		k = readl(&exynos_clock->epll_con1);
+		r = read32(&exynos_clock->epll_con0);
+		k = read32(&exynos_clock->epll_con1);
 		break;
 	case VPLL:
-		r = readl(&exynos_clock->vpll_con0);
-		k = readl(&exynos_clock->vpll_con1);
+		r = read32(&exynos_clock->vpll_con0);
+		k = read32(&exynos_clock->vpll_con1);
 		break;
 	default:
 		printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
@@ -246,41 +246,41 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 	case PERIPH_ID_UART1:
 	case PERIPH_ID_UART2:
 	case PERIPH_ID_UART3:
-		src = readl(&exynos_clock->src_peric0);
-		div = readl(&exynos_clock->div_peric0);
+		src = read32(&exynos_clock->src_peric0);
+		div = read32(&exynos_clock->div_peric0);
 		break;
 	case PERIPH_ID_PWM0:
 	case PERIPH_ID_PWM1:
 	case PERIPH_ID_PWM2:
 	case PERIPH_ID_PWM3:
 	case PERIPH_ID_PWM4:
-		src = readl(&exynos_clock->src_peric0);
-		div = readl(&exynos_clock->div_peric3);
+		src = read32(&exynos_clock->src_peric0);
+		div = read32(&exynos_clock->div_peric3);
 		break;
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
-		src = readl(&exynos_clock->src_peric1);
-		div = readl(&exynos_clock->div_peric1);
+		src = read32(&exynos_clock->src_peric1);
+		div = read32(&exynos_clock->div_peric1);
 		break;
 	case PERIPH_ID_SPI2:
-		src = readl(&exynos_clock->src_peric1);
-		div = readl(&exynos_clock->div_peric2);
+		src = read32(&exynos_clock->src_peric1);
+		div = read32(&exynos_clock->div_peric2);
 		break;
 	case PERIPH_ID_SPI3:
 	case PERIPH_ID_SPI4:
-		src = readl(&exynos_clock->sclk_src_isp);
-		div = readl(&exynos_clock->sclk_div_isp);
+		src = read32(&exynos_clock->sclk_src_isp);
+		div = read32(&exynos_clock->sclk_div_isp);
 		break;
 	case PERIPH_ID_SATA:
-		src = readl(&exynos_clock->src_fsys);
-		div = readl(&exynos_clock->div_fsys0);
+		src = read32(&exynos_clock->src_fsys);
+		div = read32(&exynos_clock->div_fsys0);
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC2:
 	case PERIPH_ID_SDMMC3:
-		src = readl(&exynos_clock->src_fsys);
-		div = readl(&exynos_clock->div_fsys1);
+		src = read32(&exynos_clock->src_fsys);
+		div = read32(&exynos_clock->div_fsys1);
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -291,9 +291,9 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 	case PERIPH_ID_I2C6:
 	case PERIPH_ID_I2C7:
 		sclk = get_pll_clk(MPLL);
-		sub_div = ((readl(&exynos_clock->div_top1)
+		sub_div = ((read32(&exynos_clock->div_top1)
 			    >> bit_info->div_bit) & 0x7) + 1;
-		div = ((readl(&exynos_clock->div_top0)
+		div = ((read32(&exynos_clock->div_top0)
 		        >> bit_info->prediv_bit) & 0x7) + 1;
 		return (sclk / sub_div) / div;
 	default:
@@ -337,7 +337,7 @@ unsigned long get_arm_clk(void)
 	unsigned int arm_ratio;
 	unsigned int arm2_ratio;
 
-	div = readl(&exynos_clock->div_cpu0);
+	div = read32(&exynos_clock->div_cpu0);
 
 	/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
 	arm_ratio = (div >> 0) & 0x7;
@@ -383,10 +383,10 @@ void set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
+	val = read32(addr);
 	val &= ~(0xff << ((dev_index << 4) + 8));
 	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	write32(addr, val);
 }
 
 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
@@ -582,10 +582,10 @@ int clock_set_mshci(enum periph_id peripheral)
 		printk(BIOS_DEBUG, "invalid peripheral\n");
 		return -1;
 	}
-	tmp = readl(addr) & ~0xff0f;
+	tmp = read32(addr) & ~0xff0f;
 	for (i = 0; i <= 0xf; i++) {
 		if ((clock / (i + 1)) <= 400) {
-			writel(tmp | i << 0, addr);
+			write32(addr, tmp | i << 0);
 			break;
 		}
 	}
@@ -599,7 +599,7 @@ int clock_epll_set_rate(unsigned long rate)
 	unsigned int lockcnt;
 	struct stopwatch sw;
 
-	epll_con = readl(&exynos_clock->epll_con0);
+	epll_con = read32(&exynos_clock->epll_con0);
 	epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
 			EPLL_CON0_LOCK_DET_EN_SHIFT) |
 		EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
@@ -627,13 +627,13 @@ int clock_epll_set_rate(unsigned long rate)
 	 */
 	lockcnt = 3000 * epll_div[i].p_div;
 
-	writel(lockcnt, &exynos_clock->epll_lock);
-	writel(epll_con, &exynos_clock->epll_con0);
-	writel(epll_con_k, &exynos_clock->epll_con1);
+	write32(&exynos_clock->epll_lock, lockcnt);
+	write32(&exynos_clock->epll_con0, epll_con);
+	write32(&exynos_clock->epll_con1, epll_con_k);
 
 	stopwatch_init_msecs_expire(&sw, TIMEOUT_EPLL_LOCK);
 
-	while (!(readl(&exynos_clock->epll_con0) &
+	while (!(read32(&exynos_clock->epll_con0) &
 			(0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
 		if (stopwatch_expired(&sw)) {
 			printk(BIOS_DEBUG,
diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c
index 409230180b..9cdd729f57 100644
--- a/src/soc/samsung/exynos5250/clock_init.c
+++ b/src/soc/samsung/exynos5250/clock_init.c
@@ -35,12 +35,12 @@ void system_clock_init(struct mem_timings *mem,
 
 	clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK);
 	do {
-		val = readl(&exynos_clock->mux_stat_cpu);
+		val = read32(&exynos_clock->mux_stat_cpu);
 	} while ((val | MUX_APLL_SEL_MASK) != val);
 
 	clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK);
 	do {
-		val = readl(&exynos_clock->mux_stat_core1);
+		val = read32(&exynos_clock->mux_stat_core1);
 	} while ((val | MUX_MPLL_SEL_MASK) != val);
 
 	clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK);
@@ -50,34 +50,34 @@ void system_clock_init(struct mem_timings *mem,
 	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
 		| MUX_GPLL_SEL_MASK;
 	do {
-		val = readl(&exynos_clock->mux_stat_top2);
+		val = read32(&exynos_clock->mux_stat_top2);
 	} while ((val | tmp) != val);
 
 	clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK);
 	do {
-		val = readl(&exynos_clock->mux_stat_cdrex);
+		val = read32(&exynos_clock->mux_stat_cdrex);
 	} while ((val | MUX_BPLL_SEL_MASK) != val);
 
 	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);
+	write32(&exynos_clock->apll_lock, APLL_LOCK_VAL);
 
-	writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);
+	write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL);
 
-	writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);
+	write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL);
 
-	writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);
+	write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL);
 
-	writel(GPLL_LOCK_VAL, &exynos_clock->gpll_lock);
+	write32(&exynos_clock->gpll_lock, GPLL_LOCK_VAL);
 
-	writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);
+	write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL);
 
-	writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);
+	write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL);
 
-	writel(CLK_REG_DISABLE, &exynos_clock->pll_div2_sel);
+	write32(&exynos_clock->pll_div2_sel, CLK_REG_DISABLE);
 
-	writel(MUX_HPM_SEL_MASK, &exynos_clock->src_cpu);
+	write32(&exynos_clock->src_cpu, MUX_HPM_SEL_MASK);
 	do {
-		val = readl(&exynos_clock->mux_stat_cpu);
+		val = read32(&exynos_clock->mux_stat_cpu);
 	} while ((val | HPM_SEL_SCLK_MPLL) != val);
 
 	val = arm_clk_ratio->arm2_ratio << 28
@@ -88,35 +88,35 @@ void system_clock_init(struct mem_timings *mem,
 		| arm_clk_ratio->acp_ratio << 8
 		| arm_clk_ratio->cpud_ratio << 4
 		| arm_clk_ratio->arm_ratio;
-	writel(val, &exynos_clock->div_cpu0);
+	write32(&exynos_clock->div_cpu0, val);
 	do {
-		val = readl(&exynos_clock->div_stat_cpu0);
+		val = read32(&exynos_clock->div_stat_cpu0);
 	} while (0 != val);
 
-	writel(CLK_DIV_CPU1_VAL, &exynos_clock->div_cpu1);
+	write32(&exynos_clock->div_cpu1, CLK_DIV_CPU1_VAL);
 	do {
-		val = readl(&exynos_clock->div_stat_cpu1);
+		val = read32(&exynos_clock->div_stat_cpu1);
 	} while (0 != val);
 
 	/* switch A15 clock source to OSC clock before changing APLL */
 	clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
 
 	/* Set APLL */
-	writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
+	write32(&exynos_clock->apll_con1, APLL_CON1_VAL);
 	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
 			arm_clk_ratio->apll_sdiv);
-	writel(val, &exynos_clock->apll_con0);
-	while ((readl(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
+	write32(&exynos_clock->apll_con0, val);
+	while ((read32(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
 		;
 
 	/* now it is safe to switch to APLL */
 	setbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
 
 	/* Set MPLL */
-	writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
+	write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL);
 	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
-	writel(val, &exynos_clock->mpll_con0);
-	while ((readl(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
+	write32(&exynos_clock->mpll_con0, val);
+	while ((read32(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
 		;
 
 	/*
@@ -127,159 +127,159 @@ void system_clock_init(struct mem_timings *mem,
 
 	/* Set BPLL */
 	if (mem->use_bpll) {
-		writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1);
+		write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL);
 		val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
-		writel(val, &exynos_clock->bpll_con0);
-		while ((readl(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0)
+		write32(&exynos_clock->bpll_con0, val);
+		while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0)
 			;
 
 		setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL);
 	}
 
 	/* Set CPLL */
-	writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1);
+	write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL);
 	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
-	writel(val, &exynos_clock->cpll_con0);
-	while ((readl(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0)
+	write32(&exynos_clock->cpll_con0, val);
+	while ((read32(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0)
 		;
 
 	/* Set GPLL */
-	writel(GPLL_CON1_VAL, &exynos_clock->gpll_con1);
+	write32(&exynos_clock->gpll_con1, GPLL_CON1_VAL);
 	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
-	writel(val, &exynos_clock->gpll_con0);
-	while ((readl(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0)
+	write32(&exynos_clock->gpll_con0, val);
+	while ((read32(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0)
 		;
 
 	/* Set EPLL */
-	writel(EPLL_CON2_VAL, &exynos_clock->epll_con2);
-	writel(EPLL_CON1_VAL, &exynos_clock->epll_con1);
+	write32(&exynos_clock->epll_con2, EPLL_CON2_VAL);
+	write32(&exynos_clock->epll_con1, EPLL_CON1_VAL);
 	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
-	writel(val, &exynos_clock->epll_con0);
-	while ((readl(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0)
+	write32(&exynos_clock->epll_con0, val);
+	while ((read32(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0)
 		;
 
 	/* Set VPLL */
-	writel(VPLL_CON2_VAL, &exynos_clock->vpll_con2);
-	writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1);
+	write32(&exynos_clock->vpll_con2, VPLL_CON2_VAL);
+	write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL);
 	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
-	writel(val, &exynos_clock->vpll_con0);
-	while ((readl(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0)
+	write32(&exynos_clock->vpll_con0, val);
+	while ((read32(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0)
 		;
 
-	writel(CLK_SRC_CORE0_VAL, &exynos_clock->src_core0);
-	writel(CLK_DIV_CORE0_VAL, &exynos_clock->div_core0);
-	while (readl(&exynos_clock->div_stat_core0) != 0)
+	write32(&exynos_clock->src_core0, CLK_SRC_CORE0_VAL);
+	write32(&exynos_clock->div_core0, CLK_DIV_CORE0_VAL);
+	while (read32(&exynos_clock->div_stat_core0) != 0)
 		;
 
-	writel(CLK_DIV_CORE1_VAL, &exynos_clock->div_core1);
-	while (readl(&exynos_clock->div_stat_core1) != 0)
+	write32(&exynos_clock->div_core1, CLK_DIV_CORE1_VAL);
+	while (read32(&exynos_clock->div_stat_core1) != 0)
 		;
 
-	writel(CLK_DIV_SYSRGT_VAL, &exynos_clock->div_sysrgt);
-	while (readl(&exynos_clock->div_stat_sysrgt) != 0)
+	write32(&exynos_clock->div_sysrgt, CLK_DIV_SYSRGT_VAL);
+	while (read32(&exynos_clock->div_stat_sysrgt) != 0)
 		;
 
-	writel(CLK_DIV_ACP_VAL, &exynos_clock->div_acp);
-	while (readl(&exynos_clock->div_stat_acp) != 0)
+	write32(&exynos_clock->div_acp, CLK_DIV_ACP_VAL);
+	while (read32(&exynos_clock->div_stat_acp) != 0)
 		;
 
-	writel(CLK_DIV_SYSLFT_VAL, &exynos_clock->div_syslft);
-	while (readl(&exynos_clock->div_stat_syslft) != 0)
+	write32(&exynos_clock->div_syslft, CLK_DIV_SYSLFT_VAL);
+	while (read32(&exynos_clock->div_stat_syslft) != 0)
 		;
 
-	writel(CLK_SRC_TOP0_VAL, &exynos_clock->src_top0);
-	writel(CLK_SRC_TOP1_VAL, &exynos_clock->src_top1);
-	writel(TOP2_VAL, &exynos_clock->src_top2);
-	writel(CLK_SRC_TOP3_VAL, &exynos_clock->src_top3);
+	write32(&exynos_clock->src_top0, CLK_SRC_TOP0_VAL);
+	write32(&exynos_clock->src_top1, CLK_SRC_TOP1_VAL);
+	write32(&exynos_clock->src_top2, TOP2_VAL);
+	write32(&exynos_clock->src_top3, CLK_SRC_TOP3_VAL);
 
-	writel(CLK_DIV_TOP0_VAL, &exynos_clock->div_top0);
-	while (readl(&exynos_clock->div_stat_top0))
+	write32(&exynos_clock->div_top0, CLK_DIV_TOP0_VAL);
+	while (read32(&exynos_clock->div_stat_top0))
 		;
 
-	writel(CLK_DIV_TOP1_VAL, &exynos_clock->div_top1);
-	while (readl(&exynos_clock->div_stat_top1))
+	write32(&exynos_clock->div_top1, CLK_DIV_TOP1_VAL);
+	while (read32(&exynos_clock->div_stat_top1))
 		;
 
-	writel(CLK_SRC_LEX_VAL, &exynos_clock->src_lex);
+	write32(&exynos_clock->src_lex, CLK_SRC_LEX_VAL);
 	while (1) {
-		val = readl(&exynos_clock->mux_stat_lex);
+		val = read32(&exynos_clock->mux_stat_lex);
 		if (val == (val | 1))
 			break;
 	}
 
-	writel(CLK_DIV_LEX_VAL, &exynos_clock->div_lex);
-	while (readl(&exynos_clock->div_stat_lex))
+	write32(&exynos_clock->div_lex, CLK_DIV_LEX_VAL);
+	while (read32(&exynos_clock->div_stat_lex))
 		;
 
-	writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
-	while (readl(&exynos_clock->div_stat_r0x))
+	write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL);
+	while (read32(&exynos_clock->div_stat_r0x))
 		;
 
-	writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
-	while (readl(&exynos_clock->div_stat_r0x))
+	write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL);
+	while (read32(&exynos_clock->div_stat_r0x))
 		;
 
-	writel(CLK_DIV_R1X_VAL, &exynos_clock->div_r1x);
-	while (readl(&exynos_clock->div_stat_r1x))
+	write32(&exynos_clock->div_r1x, CLK_DIV_R1X_VAL);
+	while (read32(&exynos_clock->div_stat_r1x))
 		;
 
 	if (mem->use_bpll) {
-		writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL |
-			MUX_MCLK_DPHY_SEL, &exynos_clock->src_cdrex);
+		write32(&exynos_clock->src_cdrex,
+			MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL);
 	} else {
-		writel(CLK_REG_DISABLE, &exynos_clock->src_cdrex);
+		write32(&exynos_clock->src_cdrex, CLK_REG_DISABLE);
 	}
 
-	writel(CLK_DIV_CDREX_VAL, &exynos_clock->div_cdrex);
-	while (readl(&exynos_clock->div_stat_cdrex))
+	write32(&exynos_clock->div_cdrex, CLK_DIV_CDREX_VAL);
+	while (read32(&exynos_clock->div_stat_cdrex))
 		;
 
-	val = readl(&exynos_clock->src_cpu);
+	val = read32(&exynos_clock->src_cpu);
 	val |= CLK_SRC_CPU_VAL;
-	writel(val, &exynos_clock->src_cpu);
+	write32(&exynos_clock->src_cpu, val);
 
-	val = readl(&exynos_clock->src_top2);
+	val = read32(&exynos_clock->src_top2);
 	val |= CLK_SRC_TOP2_VAL;
-	writel(val, &exynos_clock->src_top2);
+	write32(&exynos_clock->src_top2, val);
 
-	val = readl(&exynos_clock->src_core1);
+	val = read32(&exynos_clock->src_core1);
 	val |= CLK_SRC_CORE1_VAL;
-	writel(val, &exynos_clock->src_core1);
+	write32(&exynos_clock->src_core1, val);
 
-	writel(CLK_SRC_FSYS0_VAL, &exynos_clock->src_fsys);
-	writel(CLK_DIV_FSYS0_VAL, &exynos_clock->div_fsys0);
-	while (readl(&exynos_clock->div_stat_fsys0))
+	write32(&exynos_clock->src_fsys, CLK_SRC_FSYS0_VAL);
+	write32(&exynos_clock->div_fsys0, CLK_DIV_FSYS0_VAL);
+	while (read32(&exynos_clock->div_stat_fsys0))
 		;
 
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cpu);
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_core);
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_acp);
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_top);
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_lex);
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r0x);
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r1x);
-	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cdrex);
-
-	writel(CLK_SRC_PERIC0_VAL, &exynos_clock->src_peric0);
-	writel(CLK_DIV_PERIC0_VAL, &exynos_clock->div_peric0);
-
-	writel(CLK_SRC_PERIC1_VAL, &exynos_clock->src_peric1);
-	writel(CLK_DIV_PERIC1_VAL, &exynos_clock->div_peric1);
-	writel(CLK_DIV_PERIC2_VAL, &exynos_clock->div_peric2);
-	writel(SCLK_SRC_ISP_VAL, &exynos_clock->sclk_src_isp);
-	writel(SCLK_DIV_ISP_VAL, &exynos_clock->sclk_div_isp);
-	writel(CLK_DIV_ISP0_VAL, &exynos_clock->div_isp0);
-	writel(CLK_DIV_ISP1_VAL, &exynos_clock->div_isp1);
-	writel(CLK_DIV_ISP2_VAL, &exynos_clock->div_isp2);
+	write32(&exynos_clock->clkout_cmu_cpu, CLK_REG_DISABLE);
+	write32(&exynos_clock->clkout_cmu_core, CLK_REG_DISABLE);
+	write32(&exynos_clock->clkout_cmu_acp, CLK_REG_DISABLE);
+	write32(&exynos_clock->clkout_cmu_top, CLK_REG_DISABLE);
+	write32(&exynos_clock->clkout_cmu_lex, CLK_REG_DISABLE);
+	write32(&exynos_clock->clkout_cmu_r0x, CLK_REG_DISABLE);
+	write32(&exynos_clock->clkout_cmu_r1x, CLK_REG_DISABLE);
+	write32(&exynos_clock->clkout_cmu_cdrex, CLK_REG_DISABLE);
+
+	write32(&exynos_clock->src_peric0, CLK_SRC_PERIC0_VAL);
+	write32(&exynos_clock->div_peric0, CLK_DIV_PERIC0_VAL);
+
+	write32(&exynos_clock->src_peric1, CLK_SRC_PERIC1_VAL);
+	write32(&exynos_clock->div_peric1, CLK_DIV_PERIC1_VAL);
+	write32(&exynos_clock->div_peric2, CLK_DIV_PERIC2_VAL);
+	write32(&exynos_clock->sclk_src_isp, SCLK_SRC_ISP_VAL);
+	write32(&exynos_clock->sclk_div_isp, SCLK_DIV_ISP_VAL);
+	write32(&exynos_clock->div_isp0, CLK_DIV_ISP0_VAL);
+	write32(&exynos_clock->div_isp1, CLK_DIV_ISP1_VAL);
+	write32(&exynos_clock->div_isp2, CLK_DIV_ISP2_VAL);
 
 	/* FIMD1 SRC CLK SELECTION */
-	writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->src_disp1_0);
+	write32(&exynos_clock->src_disp1_0, CLK_SRC_DISP1_0_VAL);
 
 	val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
 		| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
 		| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
 		| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
-	writel(val, &exynos_clock->div_fsys2);
+	write32(&exynos_clock->div_fsys2, val);
 }
 
 void clock_gate(void)
diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c
index cff1466a64..d9f001a57f 100644
--- a/src/soc/samsung/exynos5250/cpu.c
+++ b/src/soc/samsung/exynos5250/cpu.c
@@ -38,7 +38,7 @@ static unsigned int cpu_rev;
 
 static void set_cpu_id(void)
 {
-	cpu_id = readl((void *)EXYNOS5_PRO_ID);
+	cpu_id = read32((void *)EXYNOS5_PRO_ID);
 	cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12));
 
 	/*
diff --git a/src/soc/samsung/exynos5250/dmc_common.c b/src/soc/samsung/exynos5250/dmc_common.c
index 17dff1ec92..2e64905d9d 100644
--- a/src/soc/samsung/exynos5250/dmc_common.c
+++ b/src/soc/samsung/exynos5250/dmc_common.c
@@ -45,19 +45,19 @@ int dmc_config_zq(struct mem_timings *mem,
 	val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
 	val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
 	val |= ZQ_CLK_DIV_EN;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	/* Disable termination */
 	if (mem->zq_mode_noterm)
 		val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	/* ZQ_MANUAL_START: Enable */
 	val |= ZQ_MANUAL_STR;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	/* ZQ_MANUAL_START: Disable */
 	val &= ~ZQ_MANUAL_STR;
@@ -67,22 +67,22 @@ int dmc_config_zq(struct mem_timings *mem,
 	 * we are looping for the ZQ_init to complete.
 	 */
 	i = ZQ_INIT_TIMEOUT;
-	while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+	while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
 		udelay(1);
 		i--;
 	}
 	if (!i)
 		return -1;
-	writel(val, &phy0_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
 
 	i = ZQ_INIT_TIMEOUT;
-	while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+	while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
 		udelay(1);
 		i--;
 	}
 	if (!i)
 		return -1;
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	return 0;
 }
@@ -93,18 +93,18 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
 
 	if (mode == DDR_MODE_DDR3) {
 		val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
-		writel(val, &dmc->phycontrol0);
+		write32(&dmc->phycontrol0, val);
 	}
 
 	/* Update DLL Information: Force DLL Resynchronization */
-	val = readl(&dmc->phycontrol0);
+	val = read32(&dmc->phycontrol0);
 	val |= FP_RSYNC;
-	writel(val, &dmc->phycontrol0);
+	write32(&dmc->phycontrol0, val);
 
 	/* Reset Force DLL Resynchronization */
-	val = readl(&dmc->phycontrol0);
+	val = read32(&dmc->phycontrol0);
 	val &= ~FP_RSYNC;
-	writel(val, &dmc->phycontrol0);
+	write32(&dmc->phycontrol0, val);
 }
 
 void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
@@ -121,7 +121,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 
 			/* Sending NOP command */
-			writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
+			write32(&dmc->directcmd, DIRECT_CMD_NOP | mask);
 
 			/*
 			 * TODO(alim.akhtar@samsung.com): Do we need these
@@ -132,15 +132,15 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 
 			/* Sending EMRS/MRS commands */
 			for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
-				writel(mem->direct_cmd_msr[i] | mask,
-				       &dmc->directcmd);
+				write32(&dmc->directcmd,
+					mem->direct_cmd_msr[i] | mask);
 				udelay(100);
 			}
 
 			if (mem->send_zq_init) {
 				/* Sending ZQINIT command */
-				writel(DIRECT_CMD_ZQINIT | mask,
-				       &dmc->directcmd);
+				write32(&dmc->directcmd,
+					DIRECT_CMD_ZQINIT | mask);
 				/*
 				 * FIXME: This was originally sdelay(10000)
 				 * in the imported u-boot code. That may have
@@ -166,7 +166,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 
 			/* PALL (all banks precharge) CMD */
-			writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
+			write32(&dmc->directcmd, DIRECT_CMD_PALL | mask);
 			udelay(100);
 		}
 	}
@@ -174,8 +174,8 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
 
 void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
 {
-	writel(mem->memconfig, &dmc->memconfig0);
-	writel(mem->memconfig, &dmc->memconfig1);
-	writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
-	writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
+	write32(&dmc->memconfig0, mem->memconfig);
+	write32(&dmc->memconfig1, mem->memconfig);
+	write32(&dmc->membaseconfig0, DMC_MEMBASECONFIG0_VAL);
+	write32(&dmc->membaseconfig1, DMC_MEMBASECONFIG1_VAL);
 }
diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
index 3b26c206c1..5a3cf3ef06 100644
--- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
@@ -31,8 +31,10 @@
 
 static void reset_phy_ctrl(void)
 {
-	writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &exynos_clock->lpddr3phy_ctrl);
-	writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &exynos_clock->lpddr3phy_ctrl);
+	write32(&exynos_clock->lpddr3phy_ctrl,
+		LPDDR3PHY_CTRL_PHY_RESET_ENABLE);
+	write32(&exynos_clock->lpddr3phy_ctrl,
+		LPDDR3PHY_CTRL_PHY_RESET_DISABLE);
 
 #if 0
 	/*
@@ -65,14 +67,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
 		(mem->impedance << CA_CS_DRVR_DS_OFFSET) |
 		(mem->impedance << CA_ADR_DRVR_DS_OFFSET);
-	writel(val, &exynos_phy0_control->phy_con39);
-	writel(val, &exynos_phy1_control->phy_con39);
+	write32(&exynos_phy0_control->phy_con39, val);
+	write32(&exynos_phy1_control->phy_con39, val);
 
 	/* Set Read Latency and Burst Length for PHY0 and PHY1 */
 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
 		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
-	writel(val, &exynos_phy0_control->phy_con42);
-	writel(val, &exynos_phy1_control->phy_con42);
+	write32(&exynos_phy0_control->phy_con42, val);
+	write32(&exynos_phy1_control->phy_con42, val);
 
 	/* ZQ Calibration */
 	if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)){
@@ -81,71 +83,69 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	}
 
 	/* DQ Signal */
-	writel(mem->phy0_pulld_dqs, &exynos_phy0_control->phy_con14);
-	writel(mem->phy1_pulld_dqs, &exynos_phy1_control->phy_con14);
+	write32(&exynos_phy0_control->phy_con14, mem->phy0_pulld_dqs);
+	write32(&exynos_phy1_control->phy_con14, mem->phy1_pulld_dqs);
 
-	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
-		| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
-		&exynos_dmc->concontrol);
+	write32(&exynos_dmc->concontrol,
+		mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT));
 
 	update_reset_dll(exynos_dmc, DDR_MODE_DDR3);
 
 	/* DQS Signal */
-	writel(mem->phy0_dqs, &exynos_phy0_control->phy_con4);
-	writel(mem->phy1_dqs, &exynos_phy1_control->phy_con4);
+	write32(&exynos_phy0_control->phy_con4, mem->phy0_dqs);
+	write32(&exynos_phy1_control->phy_con4, mem->phy1_dqs);
 
-	writel(mem->phy0_dq, &exynos_phy0_control->phy_con6);
-	writel(mem->phy1_dq, &exynos_phy1_control->phy_con6);
+	write32(&exynos_phy0_control->phy_con6, mem->phy0_dq);
+	write32(&exynos_phy1_control->phy_con6, mem->phy1_dq);
 
-	writel(mem->phy0_tFS, &exynos_phy0_control->phy_con10);
-	writel(mem->phy1_tFS, &exynos_phy1_control->phy_con10);
+	write32(&exynos_phy0_control->phy_con10, mem->phy0_tFS);
+	write32(&exynos_phy1_control->phy_con10, mem->phy1_tFS);
 
 	val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
 		(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
 		(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
 		(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
-	writel(val, &exynos_phy0_control->phy_con12);
-	writel(val, &exynos_phy1_control->phy_con12);
+	write32(&exynos_phy0_control->phy_con12, val);
+	write32(&exynos_phy1_control->phy_con12, val);
 
 	/* Start DLL locking */
-	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&exynos_phy0_control->phy_con12);
-	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&exynos_phy1_control->phy_con12);
+	write32(&exynos_phy0_control->phy_con12,
+		val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT));
+	write32(&exynos_phy1_control->phy_con12,
+		val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT));
 
 	update_reset_dll(exynos_dmc, DDR_MODE_DDR3);
 
-	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&exynos_dmc->concontrol);
+	write32(&exynos_dmc->concontrol,
+		mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT));
 
 	/* Memory Channel Inteleaving Size */
-	writel(mem->iv_size, &exynos_dmc->ivcontrol);
+	write32(&exynos_dmc->ivcontrol, mem->iv_size);
 
 	/* Set DMC MEMCONTROL register */
 	val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE;
-	writel(val, &exynos_dmc->memcontrol);
+	write32(&exynos_dmc->memcontrol, val);
 
-	writel(mem->memconfig, &exynos_dmc->memconfig0);
-	writel(mem->memconfig, &exynos_dmc->memconfig1);
-	writel(mem->membaseconfig0, &exynos_dmc->membaseconfig0);
-	writel(mem->membaseconfig1, &exynos_dmc->membaseconfig1);
+	write32(&exynos_dmc->memconfig0, mem->memconfig);
+	write32(&exynos_dmc->memconfig1, mem->memconfig);
+	write32(&exynos_dmc->membaseconfig0, mem->membaseconfig0);
+	write32(&exynos_dmc->membaseconfig1, mem->membaseconfig1);
 
 	/* Precharge Configuration */
-	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&exynos_dmc->prechconfig);
+	write32(&exynos_dmc->prechconfig,
+		mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT);
 
 	/* Power Down mode Configuration */
-	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
-		mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
-		&exynos_dmc->pwrdnconfig);
+	write32(&exynos_dmc->pwrdnconfig,
+		mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT);
 
 	/* TimingRow, TimingData, TimingPower and Timingaref
 	 * values as per Memory AC parameters
 	 */
-	writel(mem->timing_ref, &exynos_dmc->timingref);
-	writel(mem->timing_row, &exynos_dmc->timingrow);
-	writel(mem->timing_data, &exynos_dmc->timingdata);
-	writel(mem->timing_power, &exynos_dmc->timingpower);
+	write32(&exynos_dmc->timingref, mem->timing_ref);
+	write32(&exynos_dmc->timingrow, mem->timing_row);
+	write32(&exynos_dmc->timingdata, mem->timing_data);
+	write32(&exynos_dmc->timingpower, mem->timing_power);
 
 	/* Send PALL command */
 	dmc_config_prech(mem, exynos_dmc);
@@ -162,19 +162,19 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	if (mem->gate_leveling_enable) {
 		val = PHY_CON0_RESET_VAL;
 		val |= P0_CMD_EN;
-		writel(val, &exynos_phy0_control->phy_con0);
-		writel(val, &exynos_phy1_control->phy_con0);
+		write32(&exynos_phy0_control->phy_con0, val);
+		write32(&exynos_phy1_control->phy_con0, val);
 
 		val = PHY_CON2_RESET_VAL;
 		val |= INIT_DESKEW_EN;
-		writel(val, &exynos_phy0_control->phy_con2);
-		writel(val, &exynos_phy1_control->phy_con2);
+		write32(&exynos_phy0_control->phy_con2, val);
+		write32(&exynos_phy1_control->phy_con2, val);
 
 		val = PHY_CON0_RESET_VAL;
 		val |= P0_CMD_EN;
 		val |= BYTE_RDLVL_EN;
-		writel(val, &exynos_phy0_control->phy_con0);
-		writel(val, &exynos_phy1_control->phy_con0);
+		write32(&exynos_phy0_control->phy_con0, val);
+		write32(&exynos_phy1_control->phy_con0, val);
 
 		val = (mem->ctrl_start_point <<
 				PHY_CON12_CTRL_START_POINT_SHIFT) |
@@ -182,30 +182,30 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
 			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
 			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
-		writel(val, &exynos_phy0_control->phy_con12);
-		writel(val, &exynos_phy1_control->phy_con12);
+		write32(&exynos_phy0_control->phy_con12, val);
+		write32(&exynos_phy1_control->phy_con12, val);
 
 		val = PHY_CON2_RESET_VAL;
 		val |= INIT_DESKEW_EN;
 		val |= RDLVL_GATE_EN;
-		writel(val, &exynos_phy0_control->phy_con2);
-		writel(val, &exynos_phy1_control->phy_con2);
+		write32(&exynos_phy0_control->phy_con2, val);
+		write32(&exynos_phy1_control->phy_con2, val);
 
 		val = PHY_CON0_RESET_VAL;
 		val |= P0_CMD_EN;
 		val |= BYTE_RDLVL_EN;
 		val |= CTRL_SHGATE;
-		writel(val, &exynos_phy0_control->phy_con0);
-		writel(val, &exynos_phy1_control->phy_con0);
+		write32(&exynos_phy0_control->phy_con0, val);
+		write32(&exynos_phy1_control->phy_con0, val);
 
 		val = PHY_CON1_RESET_VAL;
 		val &= ~(CTRL_GATEDURADJ_MASK);
-		writel(val, &exynos_phy0_control->phy_con1);
-		writel(val, &exynos_phy1_control->phy_con1);
+		write32(&exynos_phy0_control->phy_con1, val);
+		write32(&exynos_phy1_control->phy_con1, val);
 
-		writel(CTRL_RDLVL_GATE_ENABLE, &exynos_dmc->rdlvl_config);
+		write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_ENABLE);
 		i = RDLVL_COMPLETE_TIMEOUT;
-		while ((readl(&exynos_dmc->phystatus) &
+		while ((read32(&exynos_dmc->phystatus) &
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
 			/*
@@ -219,10 +219,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n");
 			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
 		}
-		writel(CTRL_RDLVL_GATE_DISABLE, &exynos_dmc->rdlvl_config);
+		write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_DISABLE);
 
-		writel(0, &exynos_phy0_control->phy_con14);
-		writel(0, &exynos_phy1_control->phy_con14);
+		write32(&exynos_phy0_control->phy_con14, 0);
+		write32(&exynos_phy1_control->phy_con14, 0);
 
 		val = (mem->ctrl_start_point <<
 				PHY_CON12_CTRL_START_POINT_SHIFT) |
@@ -231,8 +231,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
 			(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
 			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
-		writel(val, &exynos_phy0_control->phy_con12);
-		writel(val, &exynos_phy1_control->phy_con12);
+		write32(&exynos_phy0_control->phy_con12, val);
+		write32(&exynos_phy1_control->phy_con12, val);
 
 		update_reset_dll(exynos_dmc, DDR_MODE_DDR3);
 	}
@@ -240,11 +240,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	/* Send PALL command */
 	dmc_config_prech(mem, exynos_dmc);
 
-	writel(mem->memcontrol, &exynos_dmc->memcontrol);
+	write32(&exynos_dmc->memcontrol, mem->memcontrol);
 
 	/* Set DMC Concontrol and enable auto-refresh counter */
-	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
-		| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT),
-		&exynos_dmc->concontrol);
+	write32(&exynos_dmc->concontrol,
+		mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT));
 	return 0;
 }
diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c
index a2c0aa482d..75dadba022 100644
--- a/src/soc/samsung/exynos5250/dp-reg.c
+++ b/src/soc/samsung/exynos5250/dp-reg.c
@@ -35,7 +35,7 @@ void s5p_dp_reset(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	writel(RESET_DP_TX, &base->dp_tx_sw_reset);
+	write32(&base->dp_tx_sw_reset, RESET_DP_TX);
 
 	/* Stop Video */
 	clrbits_le32(&base->video_ctl_1, VIDEO_EN);
@@ -44,73 +44,73 @@ void s5p_dp_reset(struct s5p_dp_device *dp)
 	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, &base->func_en_1);
+	write32(&base->func_en_1, reg);
 
 	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 		SERDES_FIFO_FUNC_EN_N |
 		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, &base->func_en_2);
+	write32(&base->func_en_2, reg);
 
 	udelay(20);
 
 	reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
 		LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
-	writel(reg, &base->lane_map);
+	write32(&base->lane_map, reg);
 
-	writel(0x0, &base->sys_ctl_1);
-	writel(0x40, &base->sys_ctl_2);
-	writel(0x0, &base->sys_ctl_3);
-	writel(0x0, &base->sys_ctl_4);
+	write32(&base->sys_ctl_1, 0x0);
+	write32(&base->sys_ctl_2, 0x40);
+	write32(&base->sys_ctl_3, 0x0);
+	write32(&base->sys_ctl_4, 0x0);
 
-	writel(0x0, &base->pkt_send_ctl);
-	writel(0x0, &base->dp_hdcp_ctl);
+	write32(&base->pkt_send_ctl, 0x0);
+	write32(&base->dp_hdcp_ctl, 0x0);
 
-	writel(0x5e, &base->dp_hpd_deglitch_l);
-	writel(0x1a, &base->dp_hpd_deglitch_h);
+	write32(&base->dp_hpd_deglitch_l, 0x5e);
+	write32(&base->dp_hpd_deglitch_h, 0x1a);
 
-	writel(0x10, &base->dp_debug_ctl);
+	write32(&base->dp_debug_ctl, 0x10);
 
-	writel(0x0, &base->dp_phy_test);
+	write32(&base->dp_phy_test, 0x0);
 
-	writel(0x0, &base->dp_video_fifo_thrd);
-	writel(0x20, &base->dp_audio_margin);
+	write32(&base->dp_video_fifo_thrd, 0x0);
+	write32(&base->dp_audio_margin, 0x20);
 
-	writel(0x4, &base->m_vid_gen_filter_th);
-	writel(0x2, &base->m_aud_gen_filter_th);
+	write32(&base->m_vid_gen_filter_th, 0x4);
+	write32(&base->m_aud_gen_filter_th, 0x2);
 
-	writel(0x00000101, &base->soc_general_ctl);
+	write32(&base->soc_general_ctl, 0x00000101);
 
 	/* Set Analog Parameters */
-	writel(0x10, &base->analog_ctl_1);
-	writel(0x0C, &base->analog_ctl_2);
-	writel(0x85, &base->analog_ctl_3);
-	writel(0x66, &base->pll_filter_ctl_1);
-	writel(0x0, &base->tx_amp_tuning_ctl);
+	write32(&base->analog_ctl_1, 0x10);
+	write32(&base->analog_ctl_2, 0x0C);
+	write32(&base->analog_ctl_3, 0x85);
+	write32(&base->pll_filter_ctl_1, 0x66);
+	write32(&base->tx_amp_tuning_ctl, 0x0);
 
 	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL0 | INT_POL1, &base->int_ctl);
+	write32(&base->int_ctl, INT_POL0 | INT_POL1);
 
 	/* Clear pending registers */
-	writel(0xff, &base->common_int_sta_1);
-	writel(0x4f, &base->common_int_sta_2);
-	writel(0xe0, &base->common_int_sta_3);
-	writel(0xe7, &base->common_int_sta_4);
-	writel(0x63, &base->dp_int_sta);
+	write32(&base->common_int_sta_1, 0xff);
+	write32(&base->common_int_sta_2, 0x4f);
+	write32(&base->common_int_sta_3, 0xe0);
+	write32(&base->common_int_sta_4, 0xe7);
+	write32(&base->dp_int_sta, 0x63);
 
 	/* 0:mask,1: unmask */
-	writel(0x00, &base->common_int_mask_1);
-	writel(0x00, &base->common_int_mask_2);
-	writel(0x00, &base->common_int_mask_3);
-	writel(0x00, &base->common_int_mask_4);
-	writel(0x00, &base->int_sta_mask);
+	write32(&base->common_int_mask_1, 0x00);
+	write32(&base->common_int_mask_2, 0x00);
+	write32(&base->common_int_mask_3, 0x00);
+	write32(&base->common_int_mask_4, 0x00);
+	write32(&base->int_sta_mask, 0x00);
 }
 
 unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(&dp->base->dp_debug_ctl);
+	reg = read32(&dp->base->dp_debug_ctl);
 	if (reg & PLL_LOCK)
 		return PLL_LOCKED;
 	else
@@ -123,10 +123,10 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
 	struct stopwatch sw;
 	struct exynos5_dp *base = dp->base;
 
-	writel(0x00, &base->dp_phy_pd);
+	write32(&base->dp_phy_pd, 0x00);
 
 	reg = PLL_LOCK_CHG;
-	writel(reg, &base->common_int_sta_1);
+	write32(&base->common_int_sta_1, reg);
 
 	clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL));
 
@@ -159,7 +159,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp)
 
 	/* Clear interrupts related to AUX channel */
 	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, &base->dp_int_sta);
+	write32(&base->dp_int_sta, reg);
 
 	/* Disable AUX channel module */
 	setbits_le32(&base->func_en_2, AUX_FUNC_EN_N);
@@ -168,12 +168,12 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp)
 	reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT;
 	reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT;
 	reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT);
-	writel(reg, &base->aux_hw_retry_ctl) ;
+	write32(&base->aux_hw_retry_ctl, reg);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 	reg = DEFER_CTRL_EN;
 	reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT;
-	writel(reg, &base->aux_ch_defer_dtl);
+	write32(&base->aux_ch_defer_dtl, reg);
 
 	/* Enable AUX channel module */
 	clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N);
@@ -188,24 +188,24 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
 	setbits_le32(&base->aux_ch_ctl_2, AUX_EN);
 
 	/* Is AUX CH command reply received? */
-	reg = readl(&base->dp_int_sta);
+	reg = read32(&base->dp_int_sta);
 	while (!(reg & RPLY_RECEIV))
-		reg = readl(&base->dp_int_sta);
+		reg = read32(&base->dp_int_sta);
 
 	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, &base->dp_int_sta);
+	write32(&base->dp_int_sta, RPLY_RECEIV);
 
 	/* Clear interrupt source for AUX CH access error */
-	reg = readl(&base->dp_int_sta);
+	reg = read32(&base->dp_int_sta);
 	if (reg & AUX_ERR) {
 		printk(BIOS_ERR, "%s: AUX_ERR encountered, dp_int_sta: "
 				"0x%02x\n", __func__, reg);
-		writel(AUX_ERR, &base->dp_int_sta);
+		write32(&base->dp_int_sta, AUX_ERR);
 		return -1;
 	}
 
 	/* Check AUX CH error access status */
-	reg = readl(&base->dp_int_sta);
+	reg = read32(&base->dp_int_sta);
 	if ((reg & AUX_STATUS_MASK) != 0) {
 		printk(BIOS_ERR, "AUX CH error happens: %d\n\n",
 			reg & AUX_STATUS_MASK);
@@ -226,22 +226,22 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
 
 	for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
 		/* Clear AUX CH data buffer */
-		writel(BUF_CLR, &base->buf_data_ctl);
+		write32(&base->buf_data_ctl, BUF_CLR);
 
 		/* Select DPCD device address */
 		reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
 		reg &= AUX_ADDR_7_0_MASK;
-		writel(reg, &base->aux_addr_7_0);
+		write32(&base->aux_addr_7_0, reg);
 		reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
 		reg &= AUX_ADDR_15_8_MASK;
-		writel(reg, &base->aux_addr_15_8);
+		write32(&base->aux_addr_15_8, reg);
 		reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
 		reg &= AUX_ADDR_19_16_MASK;
-		writel(reg, &base->aux_addr_19_16);
+		write32(&base->aux_addr_19_16, reg);
 
 		/* Write data buffer */
 		reg = (unsigned int)data;
-		writel(reg, &base->buf_data_0);
+		write32(&base->buf_data_0, reg);
 
 		/*
 		 * Set DisplayPort transaction and write 1 byte
@@ -249,7 +249,7 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
 		 * If Bit 3 is 0, I2C transaction.
 		 */
 		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, &base->aux_ch_ctl_1);
+		write32(&base->aux_ch_ctl_1, reg);
 
 		/* Start AUX transaction */
 		retval = s5p_dp_start_aux_transaction(dp);
@@ -273,18 +273,18 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
 
 	for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) {
 		/* Clear AUX CH data buffer */
-		writel(BUF_CLR, &base->buf_data_ctl);
+		write32(&base->buf_data_ctl, BUF_CLR);
 
 		/* Select DPCD device address */
 		reg = reg_addr >> AUX_ADDR_7_0_SHIFT;
 		reg &= AUX_ADDR_7_0_MASK;
-		writel(reg, &base->aux_addr_7_0);
+		write32(&base->aux_addr_7_0, reg);
 		reg = reg_addr >> AUX_ADDR_15_8_SHIFT;
 		reg &= AUX_ADDR_15_8_MASK;
-		writel(reg, &base->aux_addr_15_8);
+		write32(&base->aux_addr_15_8, reg);
 		reg = reg_addr >> AUX_ADDR_19_16_SHIFT;
 		reg &= AUX_ADDR_19_16_MASK;
-		writel(reg, &base->aux_addr_19_16);
+		write32(&base->aux_addr_19_16, reg);
 
 		/*
 		 * Set DisplayPort transaction and read 1 byte
@@ -292,7 +292,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
 		 * If Bit 3 is 0, I2C transaction.
 		 */
 		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, &base->aux_ch_ctl_1);
+		write32(&base->aux_ch_ctl_1, reg);
 
 		/* Start AUX transaction */
 		retval = s5p_dp_start_aux_transaction(dp);
@@ -304,7 +304,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
 
 	/* Read data buffer */
 	if (!retval) {
-		reg = readl(&base->buf_data_0);
+		reg = read32(&base->buf_data_0);
 		*data = (unsigned char)(reg & 0xff);
 	}
 
@@ -317,17 +317,17 @@ void s5p_dp_init_video(struct s5p_dp_device *dp)
 	struct exynos5_dp *base = dp->base;
 
 	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, &base->common_int_sta_1);
+	write32(&base->common_int_sta_1, reg);
 
 	reg = 0x0;
-	writel(reg, &base->sys_ctl_1);
+	write32(&base->sys_ctl_1, reg);
 
 	reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT;
 	reg |= CHA_CTRL;
-	writel(reg, &base->sys_ctl_2);
+	write32(&base->sys_ctl_2, reg);
 
 	reg = 0x0;
-	writel(reg, &base->sys_ctl_3);
+	write32(&base->sys_ctl_3, reg);
 }
 
 void s5p_dp_set_video_color_format(struct s5p_dp_device *dp,
@@ -343,16 +343,16 @@ void s5p_dp_set_video_color_format(struct s5p_dp_device *dp,
 	reg = (dynamic_range << IN_D_RANGE_SHIFT) |
 		(color_depth << IN_BPC_SHIFT) |
 		(color_space << IN_COLOR_F_SHIFT);
-	writel(reg, &base->video_ctl_2);
+	write32(&base->video_ctl_2, reg);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(&base->video_ctl_3);
+	reg = read32(&base->video_ctl_3);
 	reg &= ~IN_YC_COEFFI_MASK;
 	if (coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, &base->video_ctl_3);
+	write32(&base->video_ctl_3, reg);
 }
 
 int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
@@ -360,18 +360,18 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->sys_ctl_1);
-	writel(reg, &base->sys_ctl_1);
+	reg = read32(&base->sys_ctl_1);
+	write32(&base->sys_ctl_1, reg);
 
-	reg = readl(&base->sys_ctl_1);
+	reg = read32(&base->sys_ctl_1);
 
 	if (!(reg & DET_STA))
 		return -1;
 
-	reg = readl(&base->sys_ctl_2);
-	writel(reg, &base->sys_ctl_2);
+	reg = read32(&base->sys_ctl_2);
+	write32(&base->sys_ctl_2, reg);
 
-	reg = readl(&base->sys_ctl_2);
+	reg = read32(&base->sys_ctl_2);
 
 	if (reg & CHA_STA) {
 		printk(BIOS_DEBUG, "Input stream clk is changing\n");
@@ -393,28 +393,28 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp,
 		setbits_le32(&base->sys_ctl_4, FIX_M_VID);
 
 		reg = m_value >> M_VID_0_VALUE_SHIFT;
-		writel(reg, &base->m_vid_0);
+		write32(&base->m_vid_0, reg);
 
 		reg = (m_value >> M_VID_1_VALUE_SHIFT);
-		writel(reg, &base->m_vid_1);
+		write32(&base->m_vid_1, reg);
 
 		reg = (m_value >> M_VID_2_VALUE_SHIFT);
-		writel(reg, &base->m_vid_2);
+		write32(&base->m_vid_2, reg);
 
 		reg = n_value >> N_VID_0_VALUE_SHIFT;
-		writel(reg, &base->n_vid_0);
+		write32(&base->n_vid_0, reg);
 
 		reg = (n_value >> N_VID_1_VALUE_SHIFT);
-		writel(reg, &base->n_vid_1);
+		write32(&base->n_vid_1, reg);
 
 		reg = (n_value >> N_VID_2_VALUE_SHIFT);
-		writel(reg, &base->n_vid_2);
+		write32(&base->n_vid_2, reg);
 	} else  {
 		clrbits_le32(&base->sys_ctl_4, FIX_M_VID);
 
-		writel(0x00, &base->n_vid_0);
-		writel(0x80, &base->n_vid_1);
-		writel(0x00, &base->n_vid_2);
+		write32(&base->n_vid_0, 0x00);
+		write32(&base->n_vid_1, 0x80);
+		write32(&base->n_vid_2, 0x00);
 	}
 }
 
@@ -423,10 +423,10 @@ void s5p_dp_enable_video_master(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->soc_general_ctl);
+	reg = read32(&base->soc_general_ctl);
 	reg &= ~VIDEO_MODE_MASK;
 	reg |= VIDEO_MODE_SLAVE_MODE;
-	writel(reg, &base->soc_general_ctl);
+	write32(&base->soc_general_ctl, reg);
 }
 
 int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
@@ -439,10 +439,10 @@ int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
 	stopwatch_init_msecs_expire(&sw, STREAM_ON_TIMEOUT);
 
 	do {
-		reg = readl(&base->common_int_sta_1);
+		reg = read32(&base->common_int_sta_1);
 		if (reg & VSYNC_DET) {
 			i++;
-			writel(reg | VSYNC_DET, &base->common_int_sta_1);
+			write32(&base->common_int_sta_1, reg | VSYNC_DET);
 		}
 		if (i == 4)
 			break;
@@ -462,28 +462,28 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->func_en_1);
+	reg = read32(&base->func_en_1);
 	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, &base->func_en_1);
+	write32(&base->func_en_1, reg);
 
-	reg = readl(&base->video_ctl_10);
+	reg = read32(&base->video_ctl_10);
 	reg &= ~INTERACE_SCAN_CFG;
 	reg |= (video_info->interlaced << 2);
-	writel(reg, &base->video_ctl_10);
+	write32(&base->video_ctl_10, reg);
 
-	reg = readl(&base->video_ctl_10);
+	reg = read32(&base->video_ctl_10);
 	reg &= ~VSYNC_POLARITY_CFG;
 	reg |= (video_info->v_sync_polarity << 1);
-	writel(reg, &base->video_ctl_10);
+	write32(&base->video_ctl_10, reg);
 
-	reg = readl(&base->video_ctl_10);
+	reg = read32(&base->video_ctl_10);
 	reg &= ~HSYNC_POLARITY_CFG;
 	reg |= (video_info->h_sync_polarity << 0);
-	writel(reg, &base->video_ctl_10);
+	write32(&base->video_ctl_10, reg);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, &base->soc_general_ctl);
+	write32(&base->soc_general_ctl, reg);
 }
 
 void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp)
@@ -491,7 +491,7 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	reg = readl(&base->dp_hw_link_training);
+	reg = read32(&base->dp_hw_link_training);
 	while (reg & HW_TRAINING_EN)
-		reg = readl(&base->dp_hw_link_training);
+		reg = read32(&base->dp_hw_link_training);
 }
diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c
index 3c7c5ef27b..befb0debf0 100644
--- a/src/soc/samsung/exynos5250/fb.c
+++ b/src/soc/samsung/exynos5250/fb.c
@@ -122,48 +122,48 @@ void fb_init(unsigned long int fb_size, void *lcdbase,
 
 	fb_size = ALIGN(fb_size, 4096);
 
-	writel(pd->ivclk | pd->fixvclk, &exynos_disp_ctrl->vidcon1);
+	write32(&exynos_disp_ctrl->vidcon1, pd->ivclk | pd->fixvclk);
 	val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET);
-	writel(val, &exynos_fimd->vidcon0);
+	write32(&exynos_fimd->vidcon0, val);
 
 	val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) |
 		(pd->lower_margin << V_FRONT_PORCH_OFFSET) |
 		(pd->upper_margin << V_BACK_PORCH_OFFSET);
-	writel(val, &exynos_disp_ctrl->vidtcon0);
+	write32(&exynos_disp_ctrl->vidtcon0, val);
 
 	val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) |
 		(pd->right_margin << H_FRONT_PORCH_OFFSET) |
 		(pd->left_margin << H_BACK_PORCH_OFFSET);
-	writel(val, &exynos_disp_ctrl->vidtcon1);
+	write32(&exynos_disp_ctrl->vidtcon1, val);
 
 	val = ((pd->xres - 1) << HOZVAL_OFFSET) |
 		((pd->yres - 1) << LINEVAL_OFFSET);
-	writel(val, &exynos_disp_ctrl->vidtcon2);
+	write32(&exynos_disp_ctrl->vidtcon2, val);
 
-	writel((unsigned int)lcdbase, &exynos_fimd->vidw00add0b0);
-	writel((unsigned int)lcdbase + fb_size, &exynos_fimd->vidw00add1b0);
+	write32(&exynos_fimd->vidw00add0b0, (unsigned int)lcdbase);
+	write32(&exynos_fimd->vidw00add1b0, (unsigned int)lcdbase + fb_size);
 
-	writel(pd->xres * 2, &exynos_fimd->vidw00add2);
+	write32(&exynos_fimd->vidw00add2, pd->xres * 2);
 
 	val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET);
 	val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET);
-	writel(val, &exynos_fimd->vidosd0b);
-	writel(pd->xres * pd->yres, &exynos_fimd->vidosd0c);
+	write32(&exynos_fimd->vidosd0b, val);
+	write32(&exynos_fimd->vidosd0c, pd->xres * pd->yres);
 
 	setbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN);
 
 	val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET;
 	val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN;
-	writel(val, &exynos_fimd->wincon0);
+	write32(&exynos_fimd->wincon0, val);
 
 	/* DPCLKCON_ENABLE */
-	writel(1 << 1, &exynos_fimd->dpclkcon);
+	write32(&exynos_fimd->dpclkcon, 1 << 1);
 }
 
 #ifdef UNUSED_CODE
 void exynos_fimd_disable(void)
 {
-	writel(0, &exynos_fimd->wincon0);
+	write32(&exynos_fimd->wincon0, 0);
 	clrbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN);
 }
 #endif
@@ -328,18 +328,18 @@ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp,
 	reg = pre_emphasis << PRE_EMPHASIS_SET_SHIFT;
 	switch (lane) {
 	case 0:
-		writel(reg, &base->ln0_link_trn_ctl);
+		write32(&base->ln0_link_trn_ctl, reg);
 		break;
 	case 1:
-		writel(reg, &base->ln1_link_trn_ctl);
+		write32(&base->ln1_link_trn_ctl, reg);
 		break;
 
 	case 2:
-		writel(reg, &base->ln2_link_trn_ctl);
+		write32(&base->ln2_link_trn_ctl, reg);
 		break;
 
 	case 3:
-		writel(reg, &base->ln3_link_trn_ctl);
+		write32(&base->ln3_link_trn_ctl, reg);
 		break;
 	default:
 		printk(BIOS_DEBUG, "%s: Invalid lane %d\n", __func__, lane);
@@ -432,7 +432,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
 		}
 
 	/* All DP analog module power up */
-	writel(0x00, &base->dp_phy_pd);
+	write32(&base->dp_phy_pd, 0x00);
 
 	/* Initialize by reading RX's DPCD */
 	s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
@@ -463,21 +463,21 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
 		dp->link_train.link_rate = max_rate;
 
 	/* Set link rate and count as you want to establish*/
-	writel(dp->link_train.lane_count, &base->lane_count_set);
-	writel(dp->link_train.link_rate, &base->link_bw_set);
+	write32(&base->lane_count_set, dp->link_train.lane_count);
+	write32(&base->link_bw_set, dp->link_train.link_rate);
 
 	/* Set sink to D0 (Sink Not Ready) mode. */
 	s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 				  DPCD_SET_POWER_STATE_D0);
 
 	/* Start HW link training */
-	writel(HW_TRAINING_EN, &base->dp_hw_link_training);
+	write32(&base->dp_hw_link_training, HW_TRAINING_EN);
 
 	/* Wait until HW link training done */
 	s5p_dp_wait_hw_link_training_done(dp);
 
 	/* Get hardware link training status */
-	data = readl(&base->dp_hw_link_training);
+	data = read32(&base->dp_hw_link_training);
 	printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data);
 	if (data != 0) {
 		printk(BIOS_ERR, " H/W link training failure: 0x%x\n", data);
@@ -485,11 +485,11 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
 	}
 
 	/* Get Link Bandwidth */
-	data = readl(&base->link_bw_set);
+	data = read32(&base->link_bw_set);
 
 	dp->link_train.link_rate = data;
 
-	data = readl(&base->lane_count_set);
+	data = read32(&base->lane_count_set);
 	dp->link_train.lane_count = data;
 	printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n",
 		dp->link_train.link_rate, data);
@@ -541,8 +541,8 @@ int dp_controller_init(struct s5p_dp_device *dp_device)
 	/* Enable enhanced mode */
 	setbits_le32(&base->sys_ctl_4, ENHANCED);
 
-	writel(dp->link_train.lane_count, &base->lane_count_set);
-	writel(dp->link_train.link_rate, &base->link_bw_set);
+	write32(&base->lane_count_set, dp->link_train.lane_count);
+	write32(&base->link_bw_set, dp->link_train.link_rate);
 
 	s5p_dp_init_video(dp);
 	ret = s5p_dp_config_video(dp, dp->video_info);
diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c
index 203aa03a42..c7a84197d0 100644
--- a/src/soc/samsung/exynos5250/gpio.c
+++ b/src/soc/samsung/exynos5250/gpio.c
@@ -82,10 +82,10 @@ void gpio_cfg_pin(int gpio, int cfg)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->con);
+	value = read32(&bank->con);
 	value &= ~CON_MASK(GPIO_BIT(gpio));
 	value |= CON_SFR(GPIO_BIT(gpio), cfg);
-	writel(value, &bank->con);
+	write32(&bank->con, value);
 }
 
 static int gpio_get_cfg(int gpio)
@@ -93,7 +93,7 @@ static int gpio_get_cfg(int gpio)
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 	int shift = GPIO_BIT(gpio) << 2;
 
-	return (readl(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift;
+	return (read32(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift;
 }
 
 void gpio_set_pull(int gpio, int mode)
@@ -101,7 +101,7 @@ void gpio_set_pull(int gpio, int mode)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->pull);
+	value = read32(&bank->pull);
 	value &= ~PULL_MASK(GPIO_BIT(gpio));
 
 	switch (mode) {
@@ -113,7 +113,7 @@ void gpio_set_pull(int gpio, int mode)
 		break;
 	}
 
-	writel(value, &bank->pull);
+	write32(&bank->pull, value);
 }
 
 void gpio_set_drv(int gpio, int mode)
@@ -121,7 +121,7 @@ void gpio_set_drv(int gpio, int mode)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->drv);
+	value = read32(&bank->drv);
 	value &= ~DRV_MASK(GPIO_BIT(gpio));
 
 	switch (mode) {
@@ -135,7 +135,7 @@ void gpio_set_drv(int gpio, int mode)
 		return;
 	}
 
-	writel(value, &bank->drv);
+	write32(&bank->drv, value);
 }
 
 void gpio_set_rate(int gpio, int mode)
@@ -143,7 +143,7 @@ void gpio_set_rate(int gpio, int mode)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->drv);
+	value = read32(&bank->drv);
 	value &= ~RATE_MASK(GPIO_BIT(gpio));
 
 	switch (mode) {
@@ -155,7 +155,7 @@ void gpio_set_rate(int gpio, int mode)
 		return;
 	}
 
-	writel(value, &bank->drv);
+	write32(&bank->drv, value);
 }
 
 int gpio_direction_input(unsigned gpio)
@@ -170,11 +170,11 @@ int gpio_direction_output(unsigned gpio, int value)
 	unsigned int val;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	val = readl(&bank->dat);
+	val = read32(&bank->dat);
 	val &= ~DAT_MASK(GPIO_BIT(gpio));
 	if (value)
 		val |= DAT_SET(GPIO_BIT(gpio));
-	writel(val, &bank->dat);
+	write32(&bank->dat, val);
 
 	gpio_cfg_pin(gpio, GPIO_OUTPUT);
 
@@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->dat);
+	value = read32(&bank->dat);
 	return !!(value & DAT_MASK(GPIO_BIT(gpio)));
 }
 
@@ -195,11 +195,11 @@ int gpio_set_value(unsigned gpio, int value)
 	unsigned int val;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	val = readl(&bank->dat);
+	val = read32(&bank->dat);
 	val &= ~DAT_MASK(GPIO_BIT(gpio));
 	if (value)
 		val |= DAT_SET(GPIO_BIT(gpio));
-	writel(val, &bank->dat);
+	write32(&bank->dat, val);
 
 	return 0;
 }
diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c
index f92182a77a..e9eed406e5 100644
--- a/src/soc/samsung/exynos5250/i2c.c
+++ b/src/soc/samsung/exynos5250/i2c.c
@@ -117,34 +117,34 @@ static struct s3c24x0_i2c_bus i2c_busses[] = {
 
 static int i2c_int_pending(struct i2c_regs *regs)
 {
-	return readb(&regs->con) & I2cConIntPending;
+	return read8(&regs->con) & I2cConIntPending;
 }
 
 static void i2c_clear_int(struct i2c_regs *regs)
 {
-	writeb(readb(&regs->con) & ~I2cConIntPending, &regs->con);
+	write8(&regs->con, read8(&regs->con) & ~I2cConIntPending);
 }
 
 static void i2c_ack_enable(struct i2c_regs *regs)
 {
-	writeb(readb(&regs->con) | I2cConAckGen, &regs->con);
+	write8(&regs->con, read8(&regs->con) | I2cConAckGen);
 }
 
 static void i2c_ack_disable(struct i2c_regs *regs)
 {
-	writeb(readb(&regs->con) & ~I2cConAckGen, &regs->con);
+	write8(&regs->con, read8(&regs->con) & ~I2cConAckGen);
 }
 
 static int i2c_got_ack(struct i2c_regs *regs)
 {
-	return !(readb(&regs->stat) & I2cStatAck);
+	return !(read8(&regs->stat) & I2cStatAck);
 }
 
 static int i2c_wait_for_idle(struct i2c_regs *regs)
 {
 	int timeout = 1000 * 100; // 1s.
 	while (timeout--) {
-		if (!(readb(&regs->stat) & I2cStatBusy))
+		if (!(read8(&regs->stat) & I2cStatBusy))
 			return 0;
 		udelay(10);
 	}
@@ -169,17 +169,17 @@ static int i2c_wait_for_int(struct i2c_regs *regs)
 
 static int i2c_send_stop(struct i2c_regs *regs)
 {
-	uint8_t mode = readb(&regs->stat) & (I2cStatModeMask);
-	writeb(mode | I2cStatEnable, &regs->stat);
+	uint8_t mode = read8(&regs->stat) & (I2cStatModeMask);
+	write8(&regs->stat, mode | I2cStatEnable);
 	i2c_clear_int(regs);
 	return i2c_wait_for_idle(regs);
 }
 
 static int i2c_send_start(struct i2c_regs *regs, int read, int chip)
 {
-	writeb(chip << 1, &regs->ds);
+	write8(&regs->ds, chip << 1);
 	uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit;
-	writeb(mode | I2cStatStartStop | I2cStatEnable, &regs->stat);
+	write8(&regs->stat, mode | I2cStatStartStop | I2cStatEnable);
 	i2c_clear_int(regs);
 
 	if (i2c_wait_for_int(regs))
@@ -201,7 +201,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len)
 
 	int i;
 	for (i = 0; i < len; i++) {
-		writeb(data[i], &regs->ds);
+		write8(&regs->ds, data[i]);
 
 		i2c_clear_int(regs);
 		if (i2c_wait_for_int(regs))
@@ -231,7 +231,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len)
 		if (i2c_wait_for_int(regs))
 			return 1;
 
-		data[i] = readb(&regs->ds);
+		data[i] = read8(&regs->ds);
 	}
 
 	return 0;
@@ -246,7 +246,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count)
 	if (!regs || i2c_wait_for_idle(regs))
 		return 1;
 
-	writeb(I2cStatMasterXmit | I2cStatEnable, &regs->stat);
+	write8(&regs->stat, I2cStatMasterXmit | I2cStatEnable);
 
 	int i;
 	for (i = 0; i < seg_count; i++) {
@@ -286,11 +286,11 @@ void i2c_init(unsigned bus, int speed, int slaveadd)
 
 	// Set prescaler, divisor according to freq, also set ACKGEN, IRQ.
 	val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0);
-	writel(val, &i2c->regs->con);
+	write32(&i2c->regs->con, val);
 
 	// Init to SLAVE RECEIVE mode and clear I2CADDn.
-	writel(0, &i2c->regs->stat);
-	writel(slaveadd, &i2c->regs->add);
+	write32(&i2c->regs->stat, 0);
+	write32(&i2c->regs->add, slaveadd);
 	// program Master Transmit (and implicit STOP).
-	writel(I2cStatMasterXmit | I2cStatEnable, &i2c->regs->stat);
+	write32(&i2c->regs->stat, I2cStatMasterXmit | I2cStatEnable);
 }
diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c
index c7d491dd23..1b8aaa67d1 100644
--- a/src/soc/samsung/exynos5250/power.c
+++ b/src/soc/samsung/exynos5250/power.c
@@ -89,5 +89,5 @@ void power_enable_xclkout(void)
 
 void power_release_uart_retention(void)
 {
-	writel(1 << 28, &exynos_power->padret_uart_opt);
+	write32(&exynos_power->padret_uart_opt, 1 << 28);
 }
diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c
index 33a8c740f7..fed3aa7518 100644
--- a/src/soc/samsung/exynos5250/spi.c
+++ b/src/soc/samsung/exynos5250/spi.c
@@ -46,25 +46,25 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
 	out_bytes = in_bytes = todo;
 	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
 	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
-	writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+	write32(&regs->pkt_cnt, ((todo * 8) / 32) | SPI_PACKET_CNT_EN);
 
 	while (in_bytes) {
 		uint32_t spi_sts;
 		int temp;
 
-		spi_sts = readl(&regs->spi_sts);
+		spi_sts = read32(&regs->spi_sts);
 		rx_lvl = ((spi_sts >> 15) & 0x7f);
 		tx_lvl = ((spi_sts >> 6) & 0x7f);
 		while (tx_lvl < 32 && out_bytes) {
 			// TODO The "writing" (tx) is not supported now; that's
 			// why we write garbage to keep driving FIFO clock.
 			temp = 0xffffffff;
-			writel(temp, &regs->tx_data);
+			write32(&regs->tx_data, temp);
 			out_bytes -= 4;
 			tx_lvl += 4;
 		}
 		while (rx_lvl >= 4 && in_bytes) {
-			temp = readl(&regs->rx_data);
+			temp = read32(&regs->rx_data);
 			if (rxp)
 				*rxp++ = temp;
 			in_bytes -= 4;
@@ -79,9 +79,9 @@ int exynos_spi_open(struct exynos_spi *regs)
 	/* set the spi1 GPIO */
 
 	/* set pktcnt and enable it */
-	writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+	write32(&regs->pkt_cnt, 4 | SPI_PACKET_CNT_EN);
 	/* set FB_CLK_SEL */
-	writel(SPI_FB_DELAY_180, &regs->fb_clk);
+	write32(&regs->fb_clk, SPI_FB_DELAY_180);
 	/* set CH_WIDTH and BUS_WIDTH as word */
 	setbits_le32(&regs->mode_cfg,
 		     SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
@@ -109,10 +109,10 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off)
 	clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
 
 	/* Send read instruction (0x3h) followed by a 24 bit addr */
-	writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data);
+	write32(&regs->tx_data, (SF_READ_DATA_CMD << 24) | off);
 
 	/* waiting for TX done */
-	while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE));
+	while (!(read32(&regs->spi_sts) & SPI_ST_TX_DONE));
 
 	for (upto = 0, i = 0; upto < len; upto += todo, i++) {
 		todo = MIN(len - upto, (1 << 15));
@@ -132,7 +132,7 @@ int exynos_spi_close(struct exynos_spi *regs)
 	 */
 	clrbits_le32(&regs->mode_cfg,
 		     SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
-	writel(0, &regs->swap_cfg);
+	write32(&regs->swap_cfg, 0);
 
 	/*
 	 * Flush spi tx, rx fifos and reset the SPI controller
diff --git a/src/soc/samsung/exynos5250/timer.c b/src/soc/samsung/exynos5250/timer.c
index 1e25771dbd..2abaf3bc5d 100644
--- a/src/soc/samsung/exynos5250/timer.c
+++ b/src/soc/samsung/exynos5250/timer.c
@@ -27,16 +27,15 @@ static const uint32_t clocks_per_usec = MCT_HZ/1000000;
 
 static uint64_t mct_raw_value(void)
 {
-	uint64_t upper = readl(&exynos_mct->g_cnt_u);
-	uint64_t lower = readl(&exynos_mct->g_cnt_l);
+	uint64_t upper = read32(&exynos_mct->g_cnt_u);
+	uint64_t lower = read32(&exynos_mct->g_cnt_l);
 
 	return (upper << 32) | lower;
 }
 
 void init_timer(void)
 {
-	writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
-		&exynos_mct->g_tcon);
+	write32(&exynos_mct->g_tcon, read32(&exynos_mct->g_tcon) | (0x1 << 8));
 }
 
 void timer_monotonic_get(struct mono_time *mt)
diff --git a/src/soc/samsung/exynos5250/tmu.c b/src/soc/samsung/exynos5250/tmu.c
index bde11a2550..51e7ad8894 100644
--- a/src/soc/samsung/exynos5250/tmu.c
+++ b/src/soc/samsung/exynos5250/tmu.c
@@ -80,7 +80,7 @@ static int get_cur_temp(struct tmu_info *info)
 	struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base;
 
 	/* Temperature code range between min 25 and max 125 */
-	cur_temp = readl(&reg->current_temp) & 0xff;
+	cur_temp = read32(&reg->current_temp) & 0xff;
 
 	/* Calibrate current temperature */
 	if (cur_temp)
@@ -142,10 +142,10 @@ static void tmu_setup_parameters(struct tmu_info *info)
 	struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base;
 
 	/* Must reload for using efuse value at EXYNOS */
-	writel(TRIMINFO_RELOAD, &reg->triminfo_control);
+	write32(&reg->triminfo_control, TRIMINFO_RELOAD);
 
 	/* Get the compensation parameter */
-	te_temp = readl(&reg->triminfo);
+	te_temp = read32(&reg->triminfo);
 	info->te1 = te_temp & TRIM_INFO_MASK;
 	info->te2 = ((te_temp >> 8) & TRIM_INFO_MASK);
 
@@ -169,8 +169,8 @@ static void tmu_setup_parameters(struct tmu_info *info)
 			(hwtrip_code << 24));
 
 	/* Set interrupt level */
-	writel(rising_value, &reg->threshold_temp_rise);
-	writel(cooling_temp, &reg->threshold_temp_fall);
+	write32(&reg->threshold_temp_rise, rising_value);
+	write32(&reg->threshold_temp_fall, cooling_temp);
 
 	/*
 	 * Need to init all register settings after getting parameter info
@@ -183,20 +183,20 @@ static void tmu_setup_parameters(struct tmu_info *info)
 	 * TODO(bhthompson): rewrite this code such that we are not performing
 	 * a hard wipe of tmu_control and re verify functionality.
 	 */
-	writel(data->slope, &reg->tmu_control);
+	write32(&reg->tmu_control, data->slope);
 
-	writel(INTCLEARALL, &reg->intclear);
+	write32(&reg->intclear, INTCLEARALL);
 	/* TMU core enable */
-	con = readl(&reg->tmu_control);
+	con = read32(&reg->tmu_control);
 	con |= (info->tmu_mux << 20) | THERM_TRIP_EN | CORE_EN;
 
-	writel(con, &reg->tmu_control);
+	write32(&reg->tmu_control, con);
 
 	/* Enable HW thermal trip */
 	power_enable_hw_thermal_trip();
 
 	/* LEV1 LEV2 interrupt enable */
-	writel(INTEN_RISE1 | INTEN_RISE2, &reg->inten);
+	write32(&reg->inten, INTEN_RISE1 | INTEN_RISE2);
 }
 
 /*
diff --git a/src/soc/samsung/exynos5250/trustzone.c b/src/soc/samsung/exynos5250/trustzone.c
index c4d3bc64b6..4a8141eeaf 100644
--- a/src/soc/samsung/exynos5250/trustzone.c
+++ b/src/soc/samsung/exynos5250/trustzone.c
@@ -31,14 +31,14 @@ void trustzone_init(void)
 		tzpc = (struct exynos_tzpc *)addr;
 
 		if (addr == TZPC0_BASE)
-			writel(R0SIZE, &tzpc->r0size);
+			write32(&tzpc->r0size, R0SIZE);
 
-		writel(DECPROTXSET, &tzpc->decprot0set);
-		writel(DECPROTXSET, &tzpc->decprot1set);
+		write32(&tzpc->decprot0set, DECPROTXSET);
+		write32(&tzpc->decprot1set, DECPROTXSET);
 
 		if (addr != TZPC9_BASE) {
-			writel(DECPROTXSET, &tzpc->decprot2set);
-			writel(DECPROTXSET, &tzpc->decprot3set);
+			write32(&tzpc->decprot2set, DECPROTXSET);
+			write32(&tzpc->decprot3set, DECPROTXSET);
 		}
 	}
 }
diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c
index c23cfed347..81386b7ec4 100644
--- a/src/soc/samsung/exynos5250/uart.c
+++ b/src/soc/samsung/exynos5250/uart.c
@@ -66,7 +66,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
 	uclk = clock_get_periph_rate(PERIPH_ID_UART3);
 	val = uclk / default_baudrate();
 
-	writel(val / 16 - 1, &uart->ubrdiv);
+	write32(&uart->ubrdiv, val / 16 - 1);
 
 	/*
 	 * FIXME(dhendrix): the original uart.h had a "br_rest" value which
@@ -91,12 +91,12 @@ static void exynos5_init_dev(struct s5p_uart *uart)
 	exynos_pinmux_uart3();
 
 	/* enable FIFOs */
-	writel(0x1, &uart->ufcon);
-	writel(0, &uart->umcon);
+	write32(&uart->ufcon, 0x1);
+	write32(&uart->umcon, 0);
 	/* 8N1 */
-	writel(0x3, &uart->ulcon);
+	write32(&uart->ulcon, 0x3);
 	/* No interrupts, no DMA, pure polling */
-	writel(0x245, &uart->ucon);
+	write32(&uart->ucon, 0x245);
 
 	serial_setbrg_dev(uart);
 }
@@ -117,7 +117,7 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
 	else
 		mask = 0xf;
 
-	return readl(&uart->uerstat) & mask;
+	return read32(&uart->uerstat) & mask;
 }
 
 /*
@@ -128,13 +128,13 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
 static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
 {
 	/* wait for character to arrive */
-	while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
+	while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
 					 RX_FIFO_FULL_MASK))) {
 		if (exynos5_uart_err_check(uart, 0))
 			return 0;
 	}
 
-	return readb(&uart->urxh) & 0xff;
+	return read8(&uart->urxh) & 0xff;
 }
 
 /*
@@ -143,17 +143,17 @@ static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
 static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data)
 {
 	/* wait for room in the tx FIFO */
-	while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
+	while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
 		if (exynos5_uart_err_check(uart, 1))
 			return;
 	}
 
-	writeb(data, &uart->utxh);
+	write8(&uart->utxh, data);
 }
 
 static void exynos5_uart_tx_flush(struct s5p_uart *uart)
 {
-	while (readl(&uart->ufstat) & 0x1ff0000);
+	while (read32(&uart->ufstat) & 0x1ff0000);
 }
 
 uintptr_t uart_platform_base(int idx)
diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c
index 8a91497e1f..3f6833657b 100644
--- a/src/soc/samsung/exynos5250/usb.c
+++ b/src/soc/samsung/exynos5250/usb.c
@@ -51,23 +51,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
 
 	/* Set relevant registers to default values (clearing all reset bits) */
 
-	writel(0x1 << 24 |	/* activate PHY low power states */
-	       0x4 << 19 |	/* low power delay value */
-	       0x1 << 18 |	/* activate PHY low power delay */
-	       0x1 << 17 |	/* enable SuperSpeed PHY suspend */
-	       0x1 << 1 |	/* default Tx deemphasis value */
-	       0, &dwc3->usb3pipectl);
+	write32(&dwc3->usb3pipectl,
+		0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0);
 
 	/* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */
-	writel(0x9 << 10 |	/* PHY clock turnaround for 8-bit UTMI+ */
-	       0x1 << 8 |	/* enable PHY sleep in L1 */
-	       0x1 << 6 |	/* enable PHY suspend */
-	       0, &dwc3->usb2phycfg);
-
-	writel(0x5dc << 19 |	/* suspend clock scale for 24MHz */
-	       0x1 << 16 |	/* retry SS three times (bugfix from U-Boot) */
-	       0x1 << 12 |	/* port capability HOST */
-	       0, &dwc3->ctl);
+	write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0);
+
+	write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0);
 }
 
 void setup_usb_drd_dwc3()
@@ -84,44 +74,25 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
 	setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
 
 	/* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
-	writel(1 << 6, &phy->utmi);
-
-	writel(0x88 << 23 |	/* spread spectrum refclk selector */
-	       0x1 << 20 |	/* enable spread spectrum */
-	       0x1 << 19 |	/* enable prescaler refclk */
-	       0x68 << 11 |	/* multiplier for 24MHz refclk */
-	       0x5 << 5 |	/* select 24MHz refclk (weird, from U-Boot) */
-	       0x1 << 4 |	/* power supply in normal operating mode */
-	       0x3 << 2 |	/* use external refclk (undocumented on 5420?)*/
-	       0x1 << 1 |	/* force port reset */
-	       0x1 << 0 |	/* normal operating mode */
-	       0, &phy->clkrst);
-
-	writel(0x9 << 26 |	/* LOS level */
-	       0x3 << 22 |	/* TX VREF tune */
-	       0x1 << 20 |	/* TX rise tune */
-	       0x1 << 18 |	/* TX res tune */
-	       0x3 << 13 |	/* TX HS X Vtune */
-	       0x3 << 9 |	/* TX FS/LS tune */
-	       0x3 << 6 |	/* SQRX tune */
-	       0x4 << 3 |	/* OTG tune */
-	       0x4 << 0 |	/* comp disc tune */
-	       0, &phy->param0);
-
-	writel(0x7f << 19 |	/* reserved */
-	       0x7f << 12 |	/* Tx launch amplitude */
-	       0x20 << 6 |	/* Tx deemphasis 6dB */
-	       0x1c << 0 |	/* Tx deemphasis 3.5dB (value from U-Boot) */
-	       0, &phy->param1);
+	write32(&phy->utmi, 1 << 6);
+
+	write32(&phy->clkrst,
+		0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0);
+
+	write32(&phy->param0,
+		0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0);
+
+	write32(&phy->param1,
+		0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0);
 
 	/* disable all test features */
-	writel(0, &phy->test);
+	write32(&phy->test, 0);
 
 	/* UTMI clock select? ("must be 0x1") */
-	writel(0x1 << 2, &phy->utmiclksel);
+	write32(&phy->utmiclksel, 0x1 << 2);
 
 	/* Samsung magic, undocumented (from U-Boot) */
-	writel(0x0, &phy->resume);
+	write32(&phy->resume, 0x0);
 
 	udelay(10);
 	clrbits_le32(&phy->clkrst, 0x1 << 1);  /* deassert port reset */
@@ -144,7 +115,7 @@ void setup_usb_host_phy(int hsic_gpio)
 	printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
 			hsic_gpio ? "with" : "without");
 
-	hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
+	hostphy_ctrl0 = read32(&exynos_usb_host_phy->usbphyctrl0);
 	hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
 			   HOST_CTRL0_COMMONON_N |
 			   /* HOST Phy setting */
@@ -158,7 +129,7 @@ void setup_usb_host_phy(int hsic_gpio)
 			  /* HOST Phy setting */
 			  HOST_CTRL0_LINKSWRST |
 			  HOST_CTRL0_UTMISWRST);
-	writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
+	write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0);
 	udelay(10);
 	clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
 		     HOST_CTRL0_LINKSWRST |
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c
index f6c7845c54..971364ddfe 100644
--- a/src/soc/samsung/exynos5420/clock.c
+++ b/src/soc/samsung/exynos5420/clock.c
@@ -47,34 +47,34 @@ unsigned long get_pll_clk(int pllreg)
 
 	switch (pllreg) {
 	case APLL:
-		r = readl(&exynos_clock->apll_con0);
+		r = read32(&exynos_clock->apll_con0);
 		break;
 	case MPLL:
-		r = readl(&exynos_clock->mpll_con0);
+		r = read32(&exynos_clock->mpll_con0);
 		break;
 	case EPLL:
-		r = readl(&exynos_clock->epll_con0);
-		k = readl(&exynos_clock->epll_con1);
+		r = read32(&exynos_clock->epll_con0);
+		k = read32(&exynos_clock->epll_con1);
 		break;
 	case VPLL:
-		r = readl(&exynos_clock->vpll_con0);
-		k = readl(&exynos_clock->vpll_con1);
+		r = read32(&exynos_clock->vpll_con0);
+		k = read32(&exynos_clock->vpll_con1);
 		break;
 	case BPLL:
-		r = readl(&exynos_clock->bpll_con0);
+		r = read32(&exynos_clock->bpll_con0);
 		break;
 	case RPLL:
-		r = readl(&exynos_clock->rpll_con0);
-		k = readl(&exynos_clock->rpll_con1);
+		r = read32(&exynos_clock->rpll_con0);
+		k = read32(&exynos_clock->rpll_con1);
 		break;
 	case SPLL:
-		r = readl(&exynos_clock->spll_con0);
+		r = read32(&exynos_clock->spll_con0);
 		break;
 	case CPLL:
-		r = readl(&exynos_clock->cpll_con0);
+		r = read32(&exynos_clock->cpll_con0);
 		break;
 	case DPLL:
-		r = readl(&exynos_clock->dpll_con0);
+		r = read32(&exynos_clock->dpll_con0);
 		break;
 	default:
 		printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
@@ -169,48 +169,48 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		src = (readl(&exynos_clock->clk_src_peric0) >> 4) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric0) >> 8) & 0xf;
+		src = (read32(&exynos_clock->clk_src_peric0) >> 4) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric0) >> 8) & 0xf;
 		break;
 	case PERIPH_ID_UART1:
-		src = (readl(&exynos_clock->clk_src_peric0) >> 8) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric0) >> 12) & 0xf;
+		src = (read32(&exynos_clock->clk_src_peric0) >> 8) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric0) >> 12) & 0xf;
 		break;
 	case PERIPH_ID_UART2:
-		src = (readl(&exynos_clock->clk_src_peric0) >> 12) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric0) >> 16) & 0xf;
+		src = (read32(&exynos_clock->clk_src_peric0) >> 12) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric0) >> 16) & 0xf;
 		break;
 	case PERIPH_ID_UART3:
-		src = (readl(&exynos_clock->clk_src_peric0) >> 16) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric0) >> 20) & 0xf;
+		src = (read32(&exynos_clock->clk_src_peric0) >> 16) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric0) >> 20) & 0xf;
 		break;
 	case PERIPH_ID_PWM0:
 	case PERIPH_ID_PWM1:
 	case PERIPH_ID_PWM2:
 	case PERIPH_ID_PWM3:
 	case PERIPH_ID_PWM4:
-		src = (readl(&exynos_clock->clk_src_peric0) >> 24) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric0) >> 28) & 0x7;
+		src = (read32(&exynos_clock->clk_src_peric0) >> 24) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric0) >> 28) & 0x7;
 		break;
 	case PERIPH_ID_SPI0:
-		src = (readl(&exynos_clock->clk_src_peric1) >> 20) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric1) >> 20) & 0xf;
+		src = (read32(&exynos_clock->clk_src_peric1) >> 20) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric1) >> 20) & 0xf;
 		break;
 	case PERIPH_ID_SPI1:
-		src = (readl(&exynos_clock->clk_src_peric1) >> 24) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric1) >> 24) & 0xf;
+		src = (read32(&exynos_clock->clk_src_peric1) >> 24) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric1) >> 24) & 0xf;
 		break;
 	case PERIPH_ID_SPI2:
-		src = (readl(&exynos_clock->clk_src_peric1) >> 28) & 0x7;
-		div = (readl(&exynos_clock->clk_div_peric1) >> 28) & 0xf;
+		src = (read32(&exynos_clock->clk_src_peric1) >> 28) & 0x7;
+		div = (read32(&exynos_clock->clk_div_peric1) >> 28) & 0xf;
 		break;
 	case PERIPH_ID_SPI3:	/* aka SPI0_ISP */
-		src = (readl(&exynos_clock->clk_src_isp) >> 16) & 0x7;
-		div = (readl(&exynos_clock->clk_div_isp0) >> 0) & 0x7;
+		src = (read32(&exynos_clock->clk_src_isp) >> 16) & 0x7;
+		div = (read32(&exynos_clock->clk_div_isp0) >> 0) & 0x7;
 		break;
 	case PERIPH_ID_SPI4:	/* aka SPI1_ISP */
-		src = (readl(&exynos_clock->clk_src_isp) >> 12) & 0x7;
-		div = (readl(&exynos_clock->clk_div_isp1) >> 4) & 0x7;
+		src = (read32(&exynos_clock->clk_src_isp) >> 12) & 0x7;
+		div = (read32(&exynos_clock->clk_div_isp1) >> 4) & 0x7;
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -229,7 +229,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 		 * TODO: Add a helper function like with the peripheral clock
 		 * select fields?
 		 */
-		src = (readl(&exynos_clock->clk_src_top1) >> 8) & 0x3;
+		src = (read32(&exynos_clock->clk_src_top1) >> 8) & 0x3;
 		if (src == 0x0)
 			src = CPLL;
 		else if (src == 0x1)
@@ -240,7 +240,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 			return -1;
 
 		sclk = get_pll_clk(src);
-		div = ((readl(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1;
+		div = ((read32(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1;
 		return sclk / div;
 	default:
 		printk(BIOS_DEBUG, "%s: invalid peripheral %d",
@@ -267,7 +267,7 @@ unsigned long get_arm_clk(void)
 	unsigned int arm_ratio;
 	unsigned int arm2_ratio;
 
-	div = readl(&exynos_clock->clk_div_cpu0);
+	div = read32(&exynos_clock->clk_div_cpu0);
 
 	/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
 	arm_ratio = (div >> 0) & 0x7;
@@ -286,7 +286,7 @@ static unsigned long get_mmc_clk(int dev_index)
 	unsigned int sel, ratio;
 	int shift = 0;
 
-	sel = readl(&exynos_clock->clk_src_fsys);
+	sel = read32(&exynos_clock->clk_src_fsys);
 	sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
 
 	if (sel == 0x3)
@@ -296,7 +296,7 @@ static unsigned long get_mmc_clk(int dev_index)
 	else
 		return 0;
 
-	ratio = readl(&exynos_clock->clk_div_fsys1);
+	ratio = read32(&exynos_clock->clk_div_fsys1);
 
 	shift = dev_index * 10;
 
@@ -316,10 +316,10 @@ void set_mmc_clk(int dev_index, unsigned int div)
 	addr = &exynos_clock->clk_div_fsys1;
 	shift = dev_index * 10;
 
-	val = readl(addr);
+	val = read32(addr);
 	val &= ~(0x3ff << shift);
 	val |= (div & 0x3ff) << shift;
-	writel(val, addr);
+	write32(addr, val);
 }
 
 /* Set DW MMC Controller clock */
@@ -546,10 +546,10 @@ int clock_set_mshci(enum periph_id peripheral)
 		printk(BIOS_DEBUG, "invalid peripheral\n");
 		return -1;
 	}
-	tmp = readl(addr) & ~0xff0f;
+	tmp = read32(addr) & ~0xff0f;
 	for (i = 0; i <= 0xf; i++) {
 		if ((clock / (i + 1)) <= 400) {
-			writel(tmp | i << 0, addr);
+			write32(addr, tmp | i << 0);
 			break;
 		}
 	}
@@ -563,7 +563,7 @@ int clock_epll_set_rate(unsigned long rate)
 	unsigned int lockcnt;
 	struct stopwatch sw;
 
-	epll_con = readl(&exynos_clock->epll_con0);
+	epll_con = read32(&exynos_clock->epll_con0);
 	epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
 			EPLL_CON0_LOCK_DET_EN_SHIFT) |
 		EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
@@ -591,13 +591,13 @@ int clock_epll_set_rate(unsigned long rate)
 	 */
 	lockcnt = 3000 * epll_div[i].p_div;
 
-	writel(lockcnt, &exynos_clock->epll_lock);
-	writel(epll_con, &exynos_clock->epll_con0);
-	writel(epll_con_k, &exynos_clock->epll_con1);
+	write32(&exynos_clock->epll_lock, lockcnt);
+	write32(&exynos_clock->epll_con0, epll_con);
+	write32(&exynos_clock->epll_con1, epll_con_k);
 
 	stopwatch_init_msecs_expire(&sw, TIMEOUT_EPLL_LOCK);
 
-	while (!(readl(&exynos_clock->epll_con0) &
+	while (!(read32(&exynos_clock->epll_con0) &
 			(0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
 		if (stopwatch_expired(&sw)) {
 			printk(BIOS_DEBUG, "%s: Timeout waiting for EPLL lock\n", __func__);
diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c
index 25b8beecd1..c5b4aaaa3f 100644
--- a/src/soc/samsung/exynos5420/clock_init.c
+++ b/src/soc/samsung/exynos5420/clock_init.c
@@ -35,186 +35,186 @@ void system_clock_init(void)
 	exynos_mct->g_tcon |= (1 << 8);
 
 	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);
-	writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);
-	writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);
-	writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);
-	writel(DPLL_LOCK_VAL, &exynos_clock->dpll_lock);
-	writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);
-	writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);
-	writel(IPLL_LOCK_VAL, &exynos_clock->ipll_lock);
-	writel(SPLL_LOCK_VAL, &exynos_clock->spll_lock);
-	writel(KPLL_LOCK_VAL, &exynos_clock->kpll_lock);
-        writel(RPLL_LOCK_VAL, &exynos_clock->rpll_lock);
+	write32(&exynos_clock->apll_lock, APLL_LOCK_VAL);
+	write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL);
+	write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL);
+	write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL);
+	write32(&exynos_clock->dpll_lock, DPLL_LOCK_VAL);
+	write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL);
+	write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL);
+	write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL);
+	write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL);
+	write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL);
+        write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
 
 	setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
 
-	writel(0, &exynos_clock->clk_src_top6);
+	write32(&exynos_clock->clk_src_top6, 0);
 
-	writel(0, &exynos_clock->clk_src_cdrex);
-	writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc);
-	writel(HPM_RATIO,  &exynos_clock->clk_div_cpu1);
-	writel(CLK_DIV_CPU0_VAL, &exynos_clock->clk_div_cpu0);
+	write32(&exynos_clock->clk_src_cdrex, 0);
+	write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL);
+	write32(&exynos_clock->clk_div_cpu1, HPM_RATIO);
+	write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL);
 
 	/* switch A15 clock source to OSC clock before changing APLL */
 	clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT);
 
 	/* Set APLL */
-	writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
+	write32(&exynos_clock->apll_con1, APLL_CON1_VAL);
 	val = set_pll(225, 3, 0);	/* FOUT=1800MHz */
-	writel(val, &exynos_clock->apll_con0);
-	while ((readl(&exynos_clock->apll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->apll_con0, val);
+	while ((read32(&exynos_clock->apll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* now it is safe to switch to APLL */
 	setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT);
 
-	writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc);
-	writel(CLK_DIV_KFC_VAL, &exynos_clock->clk_div_kfc0);
+	write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL);
+	write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL);
 
 	/* switch A7 clock source to OSC clock before changing KPLL */
 	clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
 
 	/* Set KPLL*/
-	writel(KPLL_CON1_VAL, &exynos_clock->kpll_con1);
+	write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL);
 	val = set_pll(0x190, 0x4, 0x2);
-	writel(val, &exynos_clock->kpll_con0);
-	while ((readl(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->kpll_con0, val);
+	while ((read32(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* now it is safe to switch to KPLL */
 	setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
 
 	/* Set MPLL */
-	writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
+	write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL);
 	val = set_pll(0xc8, 0x3, 0x1);
-	writel(val, &exynos_clock->mpll_con0);
-	while ((readl(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->mpll_con0, val);
+	while ((read32(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set DPLL */
-	writel(DPLL_CON1_VAL, &exynos_clock->dpll_con1);
+	write32(&exynos_clock->dpll_con1, DPLL_CON1_VAL);
 	val = set_pll(0x190, 0x4, 0x2);
-	writel(val, &exynos_clock->dpll_con0);
-	while ((readl(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->dpll_con0, val);
+	while ((read32(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set EPLL */
-	writel(EPLL_CON2_VAL, &exynos_clock->epll_con2);
-	writel(EPLL_CON1_VAL, &exynos_clock->epll_con1);
+	write32(&exynos_clock->epll_con2, EPLL_CON2_VAL);
+	write32(&exynos_clock->epll_con1, EPLL_CON1_VAL);
 	val = set_pll(0x64, 0x2, 0x1);
-	writel(val, &exynos_clock->epll_con0);
-	while ((readl(&exynos_clock->epll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->epll_con0, val);
+	while ((read32(&exynos_clock->epll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set CPLL */
-	writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1);
+	write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL);
 	val = set_pll(0xde, 0x4, 0x1);
-	writel(val, &exynos_clock->cpll_con0);
-	while ((readl(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->cpll_con0, val);
+	while ((read32(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set IPLL */
-	writel(IPLL_CON1_VAL, &exynos_clock->ipll_con1);
+	write32(&exynos_clock->ipll_con1, IPLL_CON1_VAL);
 	val = set_pll(0xB9, 0x3, 0x2);
-	writel(val, &exynos_clock->ipll_con0);
-	while ((readl(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->ipll_con0, val);
+	while ((read32(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set VPLL */
-	writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1);
+	write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL);
 	val = set_pll(0xd7, 0x3, 0x2);
-	writel(val, &exynos_clock->vpll_con0);
-	while ((readl(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->vpll_con0, val);
+	while ((read32(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set BPLL */
-	writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1);
+	write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL);
 	val = set_pll(0xc8, 0x3, 0x1);
-	writel(val, &exynos_clock->bpll_con0);
-	while ((readl(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->bpll_con0, val);
+	while ((read32(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set SPLL */
-	writel(SPLL_CON1_VAL, &exynos_clock->spll_con1);
+	write32(&exynos_clock->spll_con1, SPLL_CON1_VAL);
 	val = set_pll(200, 0x3, 0x2);	/* 400MHz */
-	writel(val, &exynos_clock->spll_con0);
-	while ((readl(&exynos_clock->spll_con0) & PLL_LOCKED) == 0)
+	write32(&exynos_clock->spll_con0, val);
+	while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0)
 		;
 
         /* We use RPLL as the source for FIMD video stream clock */
-	writel(RPLL_CON1_VAL, &exynos_clock->rpll_con1);
-	writel(RPLL_CON2_VAL, &exynos_clock->rpll_con2);
+	write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL);
+	write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL);
 	/* computed by gabe from first principles; u-boot is probably
 	 * wrong again
 	 */
 	val = set_pll(0xa0, 0x3, 0x2);
-	writel(val, &exynos_clock->rpll_con0);
+	write32(&exynos_clock->rpll_con0, val);
 	/* note: this is a meaningless exercise. The hardware lock
 	 * detection does not work. So this just spins for some
 	 * time and is done. NO indication of success should attach
 	 * to this or any other spin on a con0 value.
 	 */
-	while ((readl(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0)
+	while ((read32(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0)
 		;
 
-	writel(CLK_DIV_CDREX0_VAL, &exynos_clock->clk_div_cdrex0);
-	writel(CLK_DIV_CDREX1_VAL, &exynos_clock->clk_div_cdrex1);
+	write32(&exynos_clock->clk_div_cdrex0, CLK_DIV_CDREX0_VAL);
+	write32(&exynos_clock->clk_div_cdrex1, CLK_DIV_CDREX1_VAL);
 
-	writel(CLK_SRC_TOP0_VAL, &exynos_clock->clk_src_top0);
-	writel(CLK_SRC_TOP1_VAL, &exynos_clock->clk_src_top1);
-	writel(CLK_SRC_TOP2_VAL, &exynos_clock->clk_src_top2);
-	writel(CLK_SRC_TOP7_VAL, &exynos_clock->clk_src_top7);
+	write32(&exynos_clock->clk_src_top0, CLK_SRC_TOP0_VAL);
+	write32(&exynos_clock->clk_src_top1, CLK_SRC_TOP1_VAL);
+	write32(&exynos_clock->clk_src_top2, CLK_SRC_TOP2_VAL);
+	write32(&exynos_clock->clk_src_top7, CLK_SRC_TOP7_VAL);
 
-	writel(CLK_DIV_TOP0_VAL, &exynos_clock->clk_div_top0);
-	writel(CLK_DIV_TOP1_VAL, &exynos_clock->clk_div_top1);
-	writel(CLK_DIV_TOP2_VAL, &exynos_clock->clk_div_top2);
+	write32(&exynos_clock->clk_div_top0, CLK_DIV_TOP0_VAL);
+	write32(&exynos_clock->clk_div_top1, CLK_DIV_TOP1_VAL);
+	write32(&exynos_clock->clk_div_top2, CLK_DIV_TOP2_VAL);
 
-	writel(0, &exynos_clock->clk_src_top10);
-	writel(0, &exynos_clock->clk_src_top11);
-	writel(0, &exynos_clock->clk_src_top12);
+	write32(&exynos_clock->clk_src_top10, 0);
+	write32(&exynos_clock->clk_src_top11, 0);
+	write32(&exynos_clock->clk_src_top12, 0);
 
-	writel(CLK_SRC_TOP3_VAL, &exynos_clock->clk_src_top3);
-	writel(CLK_SRC_TOP4_VAL, &exynos_clock->clk_src_top4);
-	writel(CLK_SRC_TOP5_VAL, &exynos_clock->clk_src_top5);
+	write32(&exynos_clock->clk_src_top3, CLK_SRC_TOP3_VAL);
+	write32(&exynos_clock->clk_src_top4, CLK_SRC_TOP4_VAL);
+	write32(&exynos_clock->clk_src_top5, CLK_SRC_TOP5_VAL);
 
 	/* DISP1 BLK CLK SELECTION */
-	writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->clk_src_disp10);
-	writel(CLK_DIV_DISP1_0_VAL, &exynos_clock->clk_div_disp10);
+	write32(&exynos_clock->clk_src_disp10, CLK_SRC_DISP1_0_VAL);
+	write32(&exynos_clock->clk_div_disp10, CLK_DIV_DISP1_0_VAL);
 
 	/* AUDIO BLK */
-	writel(AUDIO0_SEL_EPLL, &exynos_clock->clk_src_mau);
-	writel(DIV_MAU_VAL, &exynos_clock->clk_div_mau);
+	write32(&exynos_clock->clk_src_mau, AUDIO0_SEL_EPLL);
+	write32(&exynos_clock->clk_div_mau, DIV_MAU_VAL);
 
 	/* FSYS */
-	writel(CLK_SRC_FSYS0_VAL, &exynos_clock->clk_src_fsys);
-	writel(CLK_DIV_FSYS0_VAL, &exynos_clock->clk_div_fsys0);
-	writel(CLK_DIV_FSYS1_VAL, &exynos_clock->clk_div_fsys1);
-	writel(CLK_DIV_FSYS2_VAL, &exynos_clock->clk_div_fsys2);
-
-	writel(CLK_SRC_ISP_VAL, &exynos_clock->clk_src_isp);
-	writel(CLK_DIV_ISP0_VAL, &exynos_clock->clk_div_isp0);
-	writel(CLK_DIV_ISP1_VAL, &exynos_clock->clk_div_isp1);
-
-	writel(CLK_SRC_PERIC0_VAL, &exynos_clock->clk_src_peric0);
-	writel(CLK_SRC_PERIC1_VAL, &exynos_clock->clk_src_peric1);
-
-	writel(CLK_DIV_PERIC0_VAL, &exynos_clock->clk_div_peric0);
-	writel(CLK_DIV_PERIC1_VAL, &exynos_clock->clk_div_peric1);
-	writel(CLK_DIV_PERIC2_VAL, &exynos_clock->clk_div_peric2);
-	writel(CLK_DIV_PERIC3_VAL, &exynos_clock->clk_div_peric3);
-	writel(CLK_DIV_PERIC4_VAL, &exynos_clock->clk_div_peric4);
-
-	writel(CLK_DIV_CPERI1_VAL, &exynos_clock->clk_div_cperi1);
-
-	writel(CLK_DIV2_RATIO, &exynos_clock->clkdiv2_ratio);
-	writel(CLK_DIV4_RATIO, &exynos_clock->clkdiv4_ratio);
-	writel(CLK_DIV_G2D, &exynos_clock->clk_div_g2d);
-
-	writel(CLK_SRC_CPU_VAL, &exynos_clock->clk_src_cpu);
-	writel(CLK_SRC_TOP6_VAL, &exynos_clock->clk_src_top6);
-	writel(CLK_SRC_CDREX_VAL, &exynos_clock->clk_src_cdrex);
-	writel(CLK_SRC_KFC_VAL, &exynos_clock->clk_src_kfc);
+	write32(&exynos_clock->clk_src_fsys, CLK_SRC_FSYS0_VAL);
+	write32(&exynos_clock->clk_div_fsys0, CLK_DIV_FSYS0_VAL);
+	write32(&exynos_clock->clk_div_fsys1, CLK_DIV_FSYS1_VAL);
+	write32(&exynos_clock->clk_div_fsys2, CLK_DIV_FSYS2_VAL);
+
+	write32(&exynos_clock->clk_src_isp, CLK_SRC_ISP_VAL);
+	write32(&exynos_clock->clk_div_isp0, CLK_DIV_ISP0_VAL);
+	write32(&exynos_clock->clk_div_isp1, CLK_DIV_ISP1_VAL);
+
+	write32(&exynos_clock->clk_src_peric0, CLK_SRC_PERIC0_VAL);
+	write32(&exynos_clock->clk_src_peric1, CLK_SRC_PERIC1_VAL);
+
+	write32(&exynos_clock->clk_div_peric0, CLK_DIV_PERIC0_VAL);
+	write32(&exynos_clock->clk_div_peric1, CLK_DIV_PERIC1_VAL);
+	write32(&exynos_clock->clk_div_peric2, CLK_DIV_PERIC2_VAL);
+	write32(&exynos_clock->clk_div_peric3, CLK_DIV_PERIC3_VAL);
+	write32(&exynos_clock->clk_div_peric4, CLK_DIV_PERIC4_VAL);
+
+	write32(&exynos_clock->clk_div_cperi1, CLK_DIV_CPERI1_VAL);
+
+	write32(&exynos_clock->clkdiv2_ratio, CLK_DIV2_RATIO);
+	write32(&exynos_clock->clkdiv4_ratio, CLK_DIV4_RATIO);
+	write32(&exynos_clock->clk_div_g2d, CLK_DIV_G2D);
+
+	write32(&exynos_clock->clk_src_cpu, CLK_SRC_CPU_VAL);
+	write32(&exynos_clock->clk_src_top6, CLK_SRC_TOP6_VAL);
+	write32(&exynos_clock->clk_src_cdrex, CLK_SRC_CDREX_VAL);
+	write32(&exynos_clock->clk_src_kfc, CLK_SRC_KFC_VAL);
 }
 
 void clock_gate(void)
diff --git a/src/soc/samsung/exynos5420/dmc_common.c b/src/soc/samsung/exynos5420/dmc_common.c
index cb1546e61a..c6fe09d705 100644
--- a/src/soc/samsung/exynos5420/dmc_common.c
+++ b/src/soc/samsung/exynos5420/dmc_common.c
@@ -45,19 +45,19 @@ int dmc_config_zq(struct mem_timings *mem,
 	val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
 	val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
 	val |= ZQ_CLK_DIV_EN;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	/* Disable termination */
 	if (mem->zq_mode_noterm)
 		val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	/* ZQ_MANUAL_START: Enable */
 	val |= ZQ_MANUAL_STR;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	/* ZQ_MANUAL_START: Disable */
 	val &= ~ZQ_MANUAL_STR;
@@ -67,22 +67,22 @@ int dmc_config_zq(struct mem_timings *mem,
 	 * we are looping for the ZQ_init to complete.
 	 */
 	i = ZQ_INIT_TIMEOUT;
-	while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+	while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
 		udelay(1);
 		i--;
 	}
 	if (!i)
 		return -1;
-	writel(val, &phy0_ctrl->phy_con16);
+	write32(&phy0_ctrl->phy_con16, val);
 
 	i = ZQ_INIT_TIMEOUT;
-	while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+	while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
 		udelay(1);
 		i--;
 	}
 	if (!i)
 		return -1;
-	writel(val, &phy1_ctrl->phy_con16);
+	write32(&phy1_ctrl->phy_con16, val);
 
 	return 0;
 }
@@ -93,18 +93,18 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
 
 	if (mode == DDR_MODE_DDR3) {
 		val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
-		writel(val, &dmc->phycontrol0);
+		write32(&dmc->phycontrol0, val);
 	}
 
 	/* Update DLL Information: Force DLL Resynchronization */
-	val = readl(&dmc->phycontrol0);
+	val = read32(&dmc->phycontrol0);
 	val |= FP_RSYNC;
-	writel(val, &dmc->phycontrol0);
+	write32(&dmc->phycontrol0, val);
 
 	/* Reset Force DLL Resynchronization */
-	val = readl(&dmc->phycontrol0);
+	val = read32(&dmc->phycontrol0);
 	val &= ~FP_RSYNC;
-	writel(val, &dmc->phycontrol0);
+	write32(&dmc->phycontrol0, val);
 }
 
 void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
@@ -121,7 +121,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 
 			/* Sending NOP command */
-			writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
+			write32(&dmc->directcmd, DIRECT_CMD_NOP | mask);
 
 			/*
 			 * TODO(alim.akhtar@samsung.com): Do we need these
@@ -132,15 +132,15 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 
 			/* Sending EMRS/MRS commands */
 			for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
-				writel(mem->direct_cmd_msr[i] | mask,
-				       &dmc->directcmd);
+				write32(&dmc->directcmd,
+					mem->direct_cmd_msr[i] | mask);
 				udelay(100);
 			}
 
 			if (mem->send_zq_init) {
 				/* Sending ZQINIT command */
-				writel(DIRECT_CMD_ZQINIT | mask,
-				       &dmc->directcmd);
+				write32(&dmc->directcmd,
+					DIRECT_CMD_ZQINIT | mask);
 				/*
 				 * FIXME: This was originally sdelay(10000)
 				 * in the imported u-boot code. That may have
@@ -166,7 +166,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 
 			/* PALL (all banks precharge) CMD */
-			writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
+			write32(&dmc->directcmd, DIRECT_CMD_PALL | mask);
 			udelay(100);
 		}
 	}
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
index 8186b6dbdf..6972618ac3 100644
--- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
@@ -47,40 +47,40 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	/* Enable BYPASS mode */
 	setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN);
 
-	writel(MUX_BPLL_SEL_FOUTBPLL, &exynos_clock->clk_src_cdrex);
+	write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL);
 	do {
-		val = readl(&exynos_clock->clk_mux_stat_cdrex);
+		val = read32(&exynos_clock->clk_mux_stat_cdrex);
 		val &= BPLL_SEL_MASK;
 	} while (val != FOUTBPLL);
 
 	clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN);
 
 	/* Specify the DDR memory type as DDR3 */
-	val = readl(&exynos_phy0_control->phy_con0);
+	val = read32(&exynos_phy0_control->phy_con0);
 	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
 	val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT);
-	writel(val, &exynos_phy0_control->phy_con0);
+	write32(&exynos_phy0_control->phy_con0, val);
 
-	val = readl(&exynos_phy1_control->phy_con0);
+	val = read32(&exynos_phy1_control->phy_con0);
 	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
 	val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT);
-	writel(val, &exynos_phy1_control->phy_con0);
+	write32(&exynos_phy1_control->phy_con0, val);
 
 	/* Set Read Latency and Burst Length for PHY0 and PHY1 */
 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
 		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
-	writel(val, &exynos_phy0_control->phy_con42);
-	writel(val, &exynos_phy1_control->phy_con42);
+	write32(&exynos_phy0_control->phy_con42, val);
+	write32(&exynos_phy1_control->phy_con42, val);
 
-	val = readl(&exynos_phy0_control->phy_con26);
+	val = read32(&exynos_phy0_control->phy_con26);
 	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
 	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
-	writel(val, &exynos_phy0_control->phy_con26);
+	write32(&exynos_phy0_control->phy_con26, val);
 
-	val = readl(&exynos_phy1_control->phy_con26);
+	val = read32(&exynos_phy1_control->phy_con26);
 	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
 	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
-	writel(val, &exynos_phy1_control->phy_con26);
+	write32(&exynos_phy1_control->phy_con26, val);
 
 	/* Set Driver strength for CK, CKE, CS & CA to 0x7
 	 * Set Driver strength for Data Slice 0~3 to 0x6
@@ -89,8 +89,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
 	val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
 		(0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
-	writel(val, &exynos_phy0_control->phy_con39);
-	writel(val, &exynos_phy1_control->phy_con39);
+	write32(&exynos_phy0_control->phy_con39, val);
+	write32(&exynos_phy1_control->phy_con39, val);
 
 	/* ZQ Calibration */
 	if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control))
@@ -100,31 +100,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN);
 
 	/* DQ Signal */
-	val = readl(&exynos_phy0_control->phy_con14);
+	val = read32(&exynos_phy0_control->phy_con14);
 	val |= mem->phy0_pulld_dqs;
-	writel(val, &exynos_phy0_control->phy_con14);
-	val = readl(&exynos_phy1_control->phy_con14);
+	write32(&exynos_phy0_control->phy_con14, val);
+	val = read32(&exynos_phy1_control->phy_con14);
 	val |= mem->phy1_pulld_dqs;
-	writel(val, &exynos_phy1_control->phy_con14);
+	write32(&exynos_phy1_control->phy_con14, val);
 
 	val = MEM_TERM_EN | PHY_TERM_EN;
-	writel(val, &exynos_drex0->phycontrol0);
-	writel(val, &exynos_drex1->phycontrol0);
-
-	writel(mem->concontrol |
-		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
-		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&exynos_drex0->concontrol);
-	writel(mem->concontrol |
-		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
-		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&exynos_drex1->concontrol);
+	write32(&exynos_drex0->phycontrol0, val);
+	write32(&exynos_drex1->phycontrol0, val);
+
+	write32(&exynos_drex0->concontrol,
+		mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT));
+	write32(&exynos_drex1->concontrol,
+		mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT));
 
 	do {
-		val = readl(&exynos_drex0->phystatus);
+		val = read32(&exynos_drex0->phystatus);
 	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
 	do {
-		val = readl(&exynos_drex1->phystatus);
+		val = read32(&exynos_drex1->phystatus);
 	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
 
 	clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START);
@@ -134,41 +130,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	update_reset_dll(exynos_drex1, mem->mem_type);
 
 	/* MEMBASECONFIG0 (CS0) */
-	writel(mem->membaseconfig0, &exynos_tzasc0->membaseconfig0);
-	writel(mem->membaseconfig0, &exynos_tzasc1->membaseconfig0);
+	write32(&exynos_tzasc0->membaseconfig0, mem->membaseconfig0);
+	write32(&exynos_tzasc1->membaseconfig0, mem->membaseconfig0);
 
 	/* MEMBASECONFIG1 (CS1) */
 	if (mem->chips_per_channel == 2) {
-		writel(mem->membaseconfig1, &exynos_tzasc0->membaseconfig1);
-		writel(mem->membaseconfig1, &exynos_tzasc1->membaseconfig1);
+		write32(&exynos_tzasc0->membaseconfig1, mem->membaseconfig1);
+		write32(&exynos_tzasc1->membaseconfig1, mem->membaseconfig1);
 	}
 
 	/* Memory Channel Interleaving Size
 	 * Exynos5420 Channel interleaving = 128 bytes
 	 */
 	/* MEMCONFIG0/1 */
-	writel(mem->memconfig, &exynos_tzasc0->memconfig0);
-	writel(mem->memconfig, &exynos_tzasc1->memconfig0);
-	writel(mem->memconfig, &exynos_tzasc0->memconfig1);
-	writel(mem->memconfig, &exynos_tzasc1->memconfig1);
+	write32(&exynos_tzasc0->memconfig0, mem->memconfig);
+	write32(&exynos_tzasc1->memconfig0, mem->memconfig);
+	write32(&exynos_tzasc0->memconfig1, mem->memconfig);
+	write32(&exynos_tzasc1->memconfig1, mem->memconfig);
 
 	/* Precharge Configuration */
-	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&exynos_drex0->prechconfig0);
-	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&exynos_drex1->prechconfig0);
+	write32(&exynos_drex0->prechconfig0,
+		mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT);
+	write32(&exynos_drex1->prechconfig0,
+		mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT);
 
 	/* TimingRow, TimingData, TimingPower and Timingref
 	 * values as per Memory AC parameters
 	 */
-	writel(mem->timing_ref, &exynos_drex0->timingref);
-	writel(mem->timing_ref, &exynos_drex1->timingref);
-	writel(mem->timing_row, &exynos_drex0->timingrow);
-	writel(mem->timing_row, &exynos_drex1->timingrow);
-	writel(mem->timing_data, &exynos_drex0->timingdata);
-	writel(mem->timing_data, &exynos_drex1->timingdata);
-	writel(mem->timing_power, &exynos_drex0->timingpower);
-	writel(mem->timing_power, &exynos_drex1->timingpower);
+	write32(&exynos_drex0->timingref, mem->timing_ref);
+	write32(&exynos_drex1->timingref, mem->timing_ref);
+	write32(&exynos_drex0->timingrow, mem->timing_row);
+	write32(&exynos_drex1->timingrow, mem->timing_row);
+	write32(&exynos_drex0->timingdata, mem->timing_data);
+	write32(&exynos_drex1->timingdata, mem->timing_data);
+	write32(&exynos_drex0->timingpower, mem->timing_power);
+	write32(&exynos_drex1->timingpower, mem->timing_power);
 
 	if (reset) {
 		/* Send NOP, MRS and ZQINIT commands.
@@ -189,8 +185,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		 * release pad retention and retain the memory content until the
 		 * initialization is complete.
 		 */
-		writel(PAD_RETENTION_DRAM_COREBLK_VAL,
-		       &exynos_power->padret_dram_cblk_opt);
+		write32(&exynos_power->padret_dram_cblk_opt,
+			PAD_RETENTION_DRAM_COREBLK_VAL);
 		do {
 			ret = read32(&exynos_power->padret_dram_status);
 		} while (ret != 0x1);
@@ -201,57 +197,55 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		 */
 		for (i = 0; i < 128; i++) {
 			for (chip = 0; chip < mem->chips_to_configure; chip++) {
-				writel(DIRECT_CMD_REFA |
-					(chip << DIRECT_CMD_CHIP_SHIFT),
-					&exynos_drex0->directcmd);
-				writel(DIRECT_CMD_REFA |
-					(chip << DIRECT_CMD_CHIP_SHIFT),
-					&exynos_drex1->directcmd);
+				write32(&exynos_drex0->directcmd,
+					DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT));
+				write32(&exynos_drex1->directcmd,
+					DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT));
 			}
 		}
 	}
 
 	if (mem->gate_leveling_enable) {
 
-		writel(PHY_CON0_RESET_VAL, &exynos_phy0_control->phy_con0);
-		writel(PHY_CON0_RESET_VAL, &exynos_phy1_control->phy_con0);
+		write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL);
+		write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL);
 
 		setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN);
 		setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN);
 
 		val = PHY_CON2_RESET_VAL;
 		val |= INIT_DESKEW_EN;
-		writel(val, &exynos_phy0_control->phy_con2);
-		writel(val, &exynos_phy1_control->phy_con2);
+		write32(&exynos_phy0_control->phy_con2, val);
+		write32(&exynos_phy1_control->phy_con2, val);
 
-		val =  readl(&exynos_phy0_control->phy_con1);
+		val =  read32(&exynos_phy0_control->phy_con1);
 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
-		writel(val, &exynos_phy0_control->phy_con1);
+		write32(&exynos_phy0_control->phy_con1, val);
 
-		val =  readl(&exynos_phy1_control->phy_con1);
+		val =  read32(&exynos_phy1_control->phy_con1);
 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
-		writel(val, &exynos_phy1_control->phy_con1);
+		write32(&exynos_phy1_control->phy_con1, val);
 
-		nLockR = readl(&exynos_phy0_control->phy_con13);
+		nLockR = read32(&exynos_phy0_control->phy_con13);
 		nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2;
-		nLockR = readl(&exynos_phy0_control->phy_con12);
+		nLockR = read32(&exynos_phy0_control->phy_con12);
 		nLockR &= ~CTRL_DLL_ON;
 		nLockR |= nLockW_phy0;
-		writel(nLockR, &exynos_phy0_control->phy_con12);
+		write32(&exynos_phy0_control->phy_con12, nLockR);
 
-		nLockR = readl(&exynos_phy1_control->phy_con13);
+		nLockR = read32(&exynos_phy1_control->phy_con13);
 		nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2;
-		nLockR = readl(&exynos_phy1_control->phy_con12);
+		nLockR = read32(&exynos_phy1_control->phy_con12);
 		nLockR &= ~CTRL_DLL_ON;
 		nLockR |= nLockW_phy1;
-		writel(nLockR, &exynos_phy1_control->phy_con12);
+		write32(&exynos_phy1_control->phy_con12, nLockR);
 
 		val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
 		for (chip = 0; chip < mem->chips_to_configure; chip++) {
-			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&exynos_drex0->directcmd);
-			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&exynos_drex1->directcmd);
+			write32(&exynos_drex0->directcmd,
+				val | (chip << DIRECT_CMD_CHIP_SHIFT));
+			write32(&exynos_drex1->directcmd,
+				val | (chip << DIRECT_CMD_CHIP_SHIFT));
 		}
 
 		setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN);
@@ -260,17 +254,17 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE);
 		setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE);
 
-		val = readl(&exynos_phy0_control->phy_con1);
+		val = read32(&exynos_phy0_control->phy_con1);
 		val &= ~(CTRL_GATEDURADJ_MASK);
-		writel(val, &exynos_phy0_control->phy_con1);
+		write32(&exynos_phy0_control->phy_con1, val);
 
-		val = readl(&exynos_phy1_control->phy_con1);
+		val = read32(&exynos_phy1_control->phy_con1);
 		val &= ~(CTRL_GATEDURADJ_MASK);
-		writel(val, &exynos_phy1_control->phy_con1);
+		write32(&exynos_phy1_control->phy_con1, val);
 
-		writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex0->rdlvl_config);
+		write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_ENABLE);
 		i = TIMEOUT;
-		while (((readl(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO)
+		while (((read32(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO)
 			!= RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
 			 * TODO(waihong): Comment on how long this take to
@@ -281,11 +275,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		}
 		if (!i)
 			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-		writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex0->rdlvl_config);
+		write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_DISABLE);
 
-		writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex1->rdlvl_config);
+		write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_ENABLE);
 		i = TIMEOUT;
-		while (((readl(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO)
+		while (((read32(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO)
 			!= RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
 			 * TODO(waihong): Comment on how long this take to
@@ -296,23 +290,23 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		}
 		if (!i)
 			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-		writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex1->rdlvl_config);
+		write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_DISABLE);
 
-		writel(0, &exynos_phy0_control->phy_con14);
-		writel(0, &exynos_phy1_control->phy_con14);
+		write32(&exynos_phy0_control->phy_con14, 0);
+		write32(&exynos_phy1_control->phy_con14, 0);
 
 		val = (0x3 << DIRECT_CMD_BANK_SHIFT);
 		for (chip = 0; chip < mem->chips_to_configure; chip++) {
-			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&exynos_drex0->directcmd);
-			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&exynos_drex1->directcmd);
+			write32(&exynos_drex0->directcmd,
+				val | (chip << DIRECT_CMD_CHIP_SHIFT));
+			write32(&exynos_drex1->directcmd,
+				val | (chip << DIRECT_CMD_CHIP_SHIFT));
 		}
 
 		/* Common Settings for Leveling */
 		val = PHY_CON12_RESET_VAL;
-		writel((val + nLockW_phy0), &exynos_phy0_control->phy_con12);
-		writel((val + nLockW_phy1), &exynos_phy1_control->phy_con12);
+		write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0));
+		write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1));
 
 		setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN);
 		setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN);
@@ -322,22 +316,18 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	dmc_config_prech(mem, exynos_drex0);
 	dmc_config_prech(mem, exynos_drex1);
 
-	writel(mem->memcontrol, &exynos_drex0->memcontrol);
-	writel(mem->memcontrol, &exynos_drex1->memcontrol);
+	write32(&exynos_drex0->memcontrol, mem->memcontrol);
+	write32(&exynos_drex1->memcontrol, mem->memcontrol);
 
 	/*
 	 * Set DMC Concontrol: Enable auto-refresh counter, provide
 	 * read data fetch cycles and enable DREX auto set powerdown
 	 * for input buffer of I/O in none read memory state.
 	 */
-	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
-		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
-		DMC_CONCONTROL_IO_PD_CON(0x2),
-		&exynos_drex0->concontrol);
-	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
-		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
-		DMC_CONCONTROL_IO_PD_CON(0x2),
-		&exynos_drex1->concontrol);
+	write32(&exynos_drex0->concontrol,
+		mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2));
+	write32(&exynos_drex1->concontrol,
+		mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2));
 
 	/* Enable Clock Gating Control for DMC
 	 * this saves around 25 mw dmc power as compared to the power
diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c
index 5a3adf907e..f56148fec3 100644
--- a/src/soc/samsung/exynos5420/dp_lowlevel.c
+++ b/src/soc/samsung/exynos5420/dp_lowlevel.c
@@ -55,7 +55,7 @@ static inline unsigned long fradl(void *v) {
 
 #define lread32(a) fradl((void *)(a))
 #else
-#define lwrite32(a,b) writel((unsigned long)(a), (void *)(b))
+#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a))
 #define lread32(a) read32((void *)(a))
 #endif
 
diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c
index dfd123254c..8059f49f1a 100644
--- a/src/soc/samsung/exynos5420/fimd.c
+++ b/src/soc/samsung/exynos5420/fimd.c
@@ -47,8 +47,8 @@ static inline unsigned long fradl(void *v) {
 #define lreadl(a) fradl((void *)(a))
 
 #else
-#define lwritel(a,b) writel((unsigned long)(a), (void *)(b))
-#define lreadl(a) readl((void *)(a))
+#define lwritel(a,b) write32((void *)(b), (unsigned long)(a))
+#define lreadl(a) read32((void *)(a))
 #endif
 
 /* not sure where we want this so ... */
diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c
index 92cdc28fc0..0a53018b3f 100644
--- a/src/soc/samsung/exynos5420/gpio.c
+++ b/src/soc/samsung/exynos5420/gpio.c
@@ -82,10 +82,10 @@ void gpio_cfg_pin(int gpio, int cfg)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->con);
+	value = read32(&bank->con);
 	value &= ~CON_MASK(GPIO_BIT(gpio));
 	value |= CON_SFR(GPIO_BIT(gpio), cfg);
-	writel(value, &bank->con);
+	write32(&bank->con, value);
 }
 
 static int gpio_get_cfg(int gpio)
@@ -93,7 +93,7 @@ static int gpio_get_cfg(int gpio)
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 	int shift = GPIO_BIT(gpio) << 2;
 
-	return (readl(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift;
+	return (read32(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift;
 }
 
 void gpio_set_pull(int gpio, int mode)
@@ -101,7 +101,7 @@ void gpio_set_pull(int gpio, int mode)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->pull);
+	value = read32(&bank->pull);
 	value &= ~PULL_MASK(GPIO_BIT(gpio));
 
 	switch (mode) {
@@ -113,7 +113,7 @@ void gpio_set_pull(int gpio, int mode)
 		break;
 	}
 
-	writel(value, &bank->pull);
+	write32(&bank->pull, value);
 }
 
 void gpio_set_drv(int gpio, int mode)
@@ -121,7 +121,7 @@ void gpio_set_drv(int gpio, int mode)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->drv);
+	value = read32(&bank->drv);
 	value &= ~DRV_MASK(GPIO_BIT(gpio));
 
 	switch (mode) {
@@ -135,7 +135,7 @@ void gpio_set_drv(int gpio, int mode)
 		return;
 	}
 
-	writel(value, &bank->drv);
+	write32(&bank->drv, value);
 }
 
 void gpio_set_rate(int gpio, int mode)
@@ -143,7 +143,7 @@ void gpio_set_rate(int gpio, int mode)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->drv);
+	value = read32(&bank->drv);
 	value &= ~RATE_MASK(GPIO_BIT(gpio));
 
 	switch (mode) {
@@ -155,7 +155,7 @@ void gpio_set_rate(int gpio, int mode)
 		return;
 	}
 
-	writel(value, &bank->drv);
+	write32(&bank->drv, value);
 }
 
 int gpio_direction_input(unsigned gpio)
@@ -170,11 +170,11 @@ int gpio_direction_output(unsigned gpio, int value)
 	unsigned int val;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	val = readl(&bank->dat);
+	val = read32(&bank->dat);
 	val &= ~DAT_MASK(GPIO_BIT(gpio));
 	if (value)
 		val |= DAT_SET(GPIO_BIT(gpio));
-	writel(val, &bank->dat);
+	write32(&bank->dat, val);
 
 	gpio_cfg_pin(gpio, GPIO_OUTPUT);
 
@@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio)
 	unsigned int value;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	value = readl(&bank->dat);
+	value = read32(&bank->dat);
 	return !!(value & DAT_MASK(GPIO_BIT(gpio)));
 }
 
@@ -195,11 +195,11 @@ int gpio_set_value(unsigned gpio, int value)
 	unsigned int val;
 	struct gpio_bank *bank = gpio_get_bank(gpio);
 
-	val = readl(&bank->dat);
+	val = read32(&bank->dat);
 	val &= ~DAT_MASK(GPIO_BIT(gpio));
 	if (value)
 		val |= DAT_SET(GPIO_BIT(gpio));
-	writel(val, &bank->dat);
+	write32(&bank->dat, val);
 
 	return 0;
 }
diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c
index 28e3f0c331..1b541b7326 100644
--- a/src/soc/samsung/exynos5420/i2c.c
+++ b/src/soc/samsung/exynos5420/i2c.c
@@ -270,7 +270,7 @@ static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle,
 	 * temp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
 	 * temp1 = (TSCLK_L + TSCLK_H + 2)
 	 */
-	uint32_t flt_cycle = (readl(&regs->i2c_conf) >> 16) & 0x7;
+	uint32_t flt_cycle = (read32(&regs->i2c_conf) >> 16) & 0x7;
 	int temp = (clkin / op_clk) - 8 - 2 * flt_cycle;
 
 	// CLK_DIV max is 256.
@@ -310,18 +310,18 @@ static void hsi2c_ch_init(struct i2c_bus *i2c, unsigned int frequency)
 	uint32_t timing_sla = data_hd << 0;
 
 	// Currently operating in fast speed mode.
-	writel(timing_fs1, &regs->i2c_timing_fs1);
-	writel(timing_fs2, &regs->i2c_timing_fs2);
-	writel(timing_fs3, &regs->i2c_timing_fs3);
-	writel(timing_sla, &regs->i2c_timing_sla);
+	write32(&regs->i2c_timing_fs1, timing_fs1);
+	write32(&regs->i2c_timing_fs2, timing_fs2);
+	write32(&regs->i2c_timing_fs3, timing_fs3);
+	write32(&regs->i2c_timing_sla, timing_sla);
 
 	// Clear to enable timeout.
-	writel(readl(&regs->i2c_timeout) & ~Hsi2cTimeoutEn,
-	       &regs->i2c_timeout);
+	write32(&regs->i2c_timeout,
+		read32(&regs->i2c_timeout) & ~Hsi2cTimeoutEn);
 
-	writel(Hsi2cTrailingCount, &regs->usi_trailing_ctl);
-	writel(Hsi2cRxfifoEn | Hsi2cTxfifoEn, &regs->usi_fifo_ctl);
-	writel(readl(&regs->i2c_conf) | Hsi2cAutoMode, &regs->i2c_conf);
+	write32(&regs->usi_trailing_ctl, Hsi2cTrailingCount);
+	write32(&regs->usi_fifo_ctl, Hsi2cRxfifoEn | Hsi2cTxfifoEn);
+	write32(&regs->i2c_conf, read32(&regs->i2c_conf) | Hsi2cAutoMode);
 }
 
 static void hsi2c_reset(struct i2c_bus *i2c)
@@ -329,8 +329,8 @@ static void hsi2c_reset(struct i2c_bus *i2c)
 	struct hsi2c_regs *regs = i2c->hsregs;
 
 	// Set and clear the bit for reset.
-	writel(readl(&regs->usi_ctl) | Hsi2cSwRst, &regs->usi_ctl);
-	writel(readl(&regs->usi_ctl) & ~Hsi2cSwRst, &regs->usi_ctl);
+	write32(&regs->usi_ctl, read32(&regs->usi_ctl) | Hsi2cSwRst);
+	write32(&regs->usi_ctl, read32(&regs->usi_ctl) & ~Hsi2cSwRst);
 
 	/* FIXME: This just assumes 100KHz as a default bus freq */
 	hsi2c_ch_init(i2c, 100000);
@@ -356,13 +356,13 @@ static void i2c_ch_init(struct i2c_bus *i2c, int speed)
 
 	// Set prescaler, divisor according to freq, also set ACKGEN, IRQ.
 	val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0);
-	writel(val, &regs->con);
+	write32(&regs->con, val);
 
 	// Init to SLAVE RECEIVE mode and clear I2CADDn.
-	writel(0, &regs->stat);
-	writel(0, &regs->add);
+	write32(&regs->stat, 0);
+	write32(&regs->add, 0);
 	// program Master Transmit (and implicit STOP).
-	writel(I2cStatMasterXmit | I2cStatEnable, &regs->stat);
+	write32(&regs->stat, I2cStatMasterXmit | I2cStatEnable);
 }
 
 void i2c_init(unsigned bus, int speed, int slaveadd)
@@ -430,7 +430,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len)
 {
 	while (!hsi2c_check_transfer(regs) && len) {
 		if (!(read32(&regs->usi_fifo_stat) & Hsi2cTxFifoFull)) {
-			writel(*data++, &regs->usi_txdata);
+			write32(&regs->usi_txdata, *data++);
 			len--;
 		}
 	}
@@ -452,7 +452,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop)
 {
 	const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster;
 
-	writel(HSI2C_SLV_ADDR_MAS(seg->chip), &regs->i2c_addr);
+	write32(&regs->i2c_addr, HSI2C_SLV_ADDR_MAS(seg->chip));
 
 	/*
 	 * We really only want to stop after this transaction (I think) if the
@@ -465,14 +465,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop)
 		seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans;
 
 	if (seg->read) {
-		writel(usi_ctl | Hsi2cRxchon, &regs->usi_ctl);
-		writel(autoconf | Hsi2cReadWrite, &regs->i2c_auto_conf);
+		write32(&regs->usi_ctl, usi_ctl | Hsi2cRxchon);
+		write32(&regs->i2c_auto_conf, autoconf | Hsi2cReadWrite);
 
 		if (hsi2c_recvdata(regs, seg->buf, seg->len))
 			return -1;
 	} else {
-		writel(usi_ctl | Hsi2cTxchon, &regs->usi_ctl);
-		writel(autoconf, &regs->i2c_auto_conf);
+		write32(&regs->usi_ctl, usi_ctl | Hsi2cTxchon);
+		write32(&regs->i2c_auto_conf, autoconf);
 
 		if (hsi2c_senddata(regs, seg->buf, seg->len))
 			return -1;
@@ -481,7 +481,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop)
 	if (hsi2c_wait_for_transfer(regs) != 1)
 		return -1;
 
-	writel(Hsi2cFuncModeI2c, &regs->usi_ctl);
+	write32(&regs->usi_ctl, Hsi2cFuncModeI2c);
 	return 0;
 }
 
@@ -510,34 +510,34 @@ static int hsi2c_transfer(struct i2c_bus *i2c, struct i2c_seg *segments,
 
 static int i2c_int_pending(struct i2c_regs *regs)
 {
-	return readb(&regs->con) & I2cConIntPending;
+	return read8(&regs->con) & I2cConIntPending;
 }
 
 static void i2c_clear_int(struct i2c_regs *regs)
 {
-	writeb(readb(&regs->con) & ~I2cConIntPending, &regs->con);
+	write8(&regs->con, read8(&regs->con) & ~I2cConIntPending);
 }
 
 static void i2c_ack_enable(struct i2c_regs *regs)
 {
-	writeb(readb(&regs->con) | I2cConAckGen, &regs->con);
+	write8(&regs->con, read8(&regs->con) | I2cConAckGen);
 }
 
 static void i2c_ack_disable(struct i2c_regs *regs)
 {
-	writeb(readb(&regs->con) & ~I2cConAckGen, &regs->con);
+	write8(&regs->con, read8(&regs->con) & ~I2cConAckGen);
 }
 
 static int i2c_got_ack(struct i2c_regs *regs)
 {
-	return !(readb(&regs->stat) & I2cStatAck);
+	return !(read8(&regs->stat) & I2cStatAck);
 }
 
 static int i2c_wait_for_idle(struct i2c_regs *regs)
 {
 	int timeout = 1000 * 100; // 1s.
 	while (timeout--) {
-		if (!(readb(&regs->stat) & I2cStatBusy))
+		if (!(read8(&regs->stat) & I2cStatBusy))
 			return 0;
 		udelay(10);
 	}
@@ -562,17 +562,17 @@ static int i2c_wait_for_int(struct i2c_regs *regs)
 
 static int i2c_send_stop(struct i2c_regs *regs)
 {
-	uint8_t mode = readb(&regs->stat) & (I2cStatModeMask);
-	writeb(mode | I2cStatEnable, &regs->stat);
+	uint8_t mode = read8(&regs->stat) & (I2cStatModeMask);
+	write8(&regs->stat, mode | I2cStatEnable);
 	i2c_clear_int(regs);
 	return i2c_wait_for_idle(regs);
 }
 
 static int i2c_send_start(struct i2c_regs *regs, int read, int chip)
 {
-	writeb(chip << 1, &regs->ds);
+	write8(&regs->ds, chip << 1);
 	uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit;
-	writeb(mode | I2cStatStartStop | I2cStatEnable, &regs->stat);
+	write8(&regs->stat, mode | I2cStatStartStop | I2cStatEnable);
 	i2c_clear_int(regs);
 
 	if (i2c_wait_for_int(regs))
@@ -594,7 +594,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len)
 
 	int i;
 	for (i = 0; i < len; i++) {
-		writeb(data[i], &regs->ds);
+		write8(&regs->ds, data[i]);
 
 		i2c_clear_int(regs);
 		if (i2c_wait_for_int(regs))
@@ -624,7 +624,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len)
 		if (i2c_wait_for_int(regs))
 			return 1;
 
-		data[i] = readb(&regs->ds);
+		data[i] = read8(&regs->ds);
 	}
 
 	return 0;
@@ -642,7 +642,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
 	if (!regs || i2c_wait_for_idle(regs))
 		return 1;
 
-	writeb(I2cStatMasterXmit | I2cStatEnable, &regs->stat);
+	write8(&regs->stat, I2cStatMasterXmit | I2cStatEnable);
 
 	int i;
 	for (i = 0; i < count; i++) {
diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c
index c7d491dd23..1b8aaa67d1 100644
--- a/src/soc/samsung/exynos5420/power.c
+++ b/src/soc/samsung/exynos5420/power.c
@@ -89,5 +89,5 @@ void power_enable_xclkout(void)
 
 void power_release_uart_retention(void)
 {
-	writel(1 << 28, &exynos_power->padret_uart_opt);
+	write32(&exynos_power->padret_uart_opt, 1 << 28);
 }
diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c
index 8775bc9baf..6c8fd06f20 100644
--- a/src/soc/samsung/exynos5420/smp.c
+++ b/src/soc/samsung/exynos5420/smp.c
@@ -152,7 +152,7 @@ static void enable_smp(void)
 	actlr |= ACTLR_SMP;
 
 	/* Dummy read to assure L2 access */
-	val = readl(&exynos_power->inform0);
+	val = read32(&exynos_power->inform0);
 	val &= 0;
 	actlr |= val;
 
@@ -200,9 +200,9 @@ static void low_power_start(void)
 	/* On warm reset, because iRAM is not cleared, all cores will enter
 	 * low_power_start, not the initial address. So we need to check reset
 	 * status again, and jump to 0x0 in that case. */
-	reg_val = readl(&exynos_power->spare0);
+	reg_val = read32(&exynos_power->spare0);
 	if (reg_val != RST_FLAG_VAL) {
-		writel(0x0, VECTOR_LOW_POWER_FLAG);
+		write32(VECTOR_LOW_POWER_FLAG, 0x0);
 		jump_bx(CORE_RESET_INIT_ADDRESS);
 		/* restart cpu execution and never returns. */
 	}
@@ -211,9 +211,9 @@ static void low_power_start(void)
 	 * path, bypassing first jump address and makes final jump address 0x0,
 	 * so we try to make any core set again low_power_start address, if that
 	 * becomes zero. */
-	reg_val = readl(VECTOR_CORE_SEV_HANDLER);
+	reg_val = read32(VECTOR_CORE_SEV_HANDLER);
 	if (reg_val != (intptr_t)low_power_start) {
-		writel((intptr_t)low_power_start, VECTOR_CORE_SEV_HANDLER);
+		write32(VECTOR_CORE_SEV_HANDLER, (intptr_t)low_power_start);
 		dsb();
 		/* ask all cores to power on again. */
 		sev();
@@ -258,7 +258,7 @@ static void power_down_core(void)
 	 * S5E5420A User Manual, 8.8.1.202, ARM_CORE0_CONFIGURATION, two bits to
 	 * control power state in each power down level.
 	 */
-	writel(0x0, &exynos_power->arm_core[core_id].config);
+	write32(&exynos_power->arm_core[core_id].config, 0x0);
 
 	/* S5E5420A User Manual, 8.4.2.5, after ARM_CORE*_CONFIGURATION has been
 	 * set to zero, PMU will detect and wait for WFI then run power-down
@@ -281,15 +281,15 @@ static void configure_secondary_cores(void)
 	 * when we want to use SMP inside firmware. */
 
 	/* Clear boot reg (hotplug address) in cpu states */
-	writel(0, (void*)&exynos_cpu_states->hotplug_address);
+	write32((void *)&exynos_cpu_states->hotplug_address, 0);
 
 	/* set low_power flag and address */
-	writel((intptr_t)low_power_start, VECTOR_LOW_POWER_ADDRESS);
-	writel(RST_FLAG_VAL, VECTOR_LOW_POWER_FLAG);
-	writel(RST_FLAG_VAL, &exynos_power->spare0);
+	write32(VECTOR_LOW_POWER_ADDRESS, (intptr_t)low_power_start);
+	write32(VECTOR_LOW_POWER_FLAG, RST_FLAG_VAL);
+	write32(&exynos_power->spare0, RST_FLAG_VAL);
 
 	/* On next SEV, shutdown all cores. */
-	writel((intptr_t)power_down_core, VECTOR_CORE_SEV_HANDLER);
+	write32(VECTOR_CORE_SEV_HANDLER, (intptr_t)power_down_core);
 
 	/* Ask all cores in WFE mode to shutdown. */
 	dsb();
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 6ceb92edd2..3d71f79529 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -69,9 +69,9 @@ static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
 
 static void spi_sw_reset(struct exynos_spi *regs, int word)
 {
-	const uint32_t orig_mode_cfg = readl(&regs->mode_cfg);
+	const uint32_t orig_mode_cfg = read32(&regs->mode_cfg);
 	uint32_t mode_cfg = orig_mode_cfg;
-	const uint32_t orig_swap_cfg = readl(&regs->swap_cfg);
+	const uint32_t orig_swap_cfg = read32(&regs->swap_cfg);
 	uint32_t swap_cfg = orig_swap_cfg;
 
 	mode_cfg &= ~(SPI_MODE_CH_WIDTH_MASK | SPI_MODE_BUS_WIDTH_MASK);
@@ -89,9 +89,9 @@ static void spi_sw_reset(struct exynos_spi *regs, int word)
 	}
 
 	if (mode_cfg != orig_mode_cfg)
-		writel(mode_cfg, &regs->mode_cfg);
+		write32(&regs->mode_cfg, mode_cfg);
 	if (swap_cfg != orig_swap_cfg)
-		writel(swap_cfg, &regs->swap_cfg);
+		write32(&regs->swap_cfg, swap_cfg);
 
 	clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
 	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
@@ -106,7 +106,7 @@ void spi_init(void)
 static void exynos_spi_init(struct exynos_spi *regs)
 {
 	// Set FB_CLK_SEL.
-	writel(SPI_FB_DELAY_180, &regs->fb_clk);
+	write32(&regs->fb_clk, SPI_FB_DELAY_180);
 	// CPOL: Active high.
 	clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L);
 
@@ -157,10 +157,10 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out,
 		out_bytes = in_bytes = packets * width;
 
 		spi_sw_reset(regs, width == 4);
-		writel(packets | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+		write32(&regs->pkt_cnt, packets | SPI_PACKET_CNT_EN);
 
 		while (out_bytes || in_bytes) {
-			uint32_t spi_sts = readl(&regs->spi_sts);
+			uint32_t spi_sts = read32(&regs->spi_sts);
 			int rx_lvl = ((spi_sts >> 15) & 0x1ff);
 			int tx_lvl = ((spi_sts >> 6) & 0x1ff);
 
@@ -171,13 +171,13 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out,
 					memcpy(&data, outb, width);
 					outb += width;
 				}
-				writel(data, &regs->tx_data);
+				write32(&regs->tx_data, data);
 
 				out_bytes -= width;
 			}
 
 			if (rx_lvl >= width) {
-				uint32_t data = readl(&regs->rx_data);
+				uint32_t data = read32(&regs->rx_data);
 
 				if (inb) {
 					memcpy(inb, &data, width);
diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c
index 1e25771dbd..2abaf3bc5d 100644
--- a/src/soc/samsung/exynos5420/timer.c
+++ b/src/soc/samsung/exynos5420/timer.c
@@ -27,16 +27,15 @@ static const uint32_t clocks_per_usec = MCT_HZ/1000000;
 
 static uint64_t mct_raw_value(void)
 {
-	uint64_t upper = readl(&exynos_mct->g_cnt_u);
-	uint64_t lower = readl(&exynos_mct->g_cnt_l);
+	uint64_t upper = read32(&exynos_mct->g_cnt_u);
+	uint64_t lower = read32(&exynos_mct->g_cnt_l);
 
 	return (upper << 32) | lower;
 }
 
 void init_timer(void)
 {
-	writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
-		&exynos_mct->g_tcon);
+	write32(&exynos_mct->g_tcon, read32(&exynos_mct->g_tcon) | (0x1 << 8));
 }
 
 void timer_monotonic_get(struct mono_time *mt)
diff --git a/src/soc/samsung/exynos5420/tmu.c b/src/soc/samsung/exynos5420/tmu.c
index 8ed78bba4a..19c72fdac3 100644
--- a/src/soc/samsung/exynos5420/tmu.c
+++ b/src/soc/samsung/exynos5420/tmu.c
@@ -80,7 +80,7 @@ static int get_cur_temp(struct tmu_info *info)
 	struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base;
 
 	/* Temperature code range between min 25 and max 125 */
-	cur_temp = readl(&reg->current_temp) & 0xff;
+	cur_temp = read32(&reg->current_temp) & 0xff;
 
 	/* Calibrate current temperature */
 	if (cur_temp)
@@ -142,10 +142,10 @@ static void tmu_setup_parameters(struct tmu_info *info)
 	struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base;
 
 	/* Must reload for using efuse value at EXYNOS */
-	writel(TRIMINFO_RELOAD, &reg->triminfo_control);
+	write32(&reg->triminfo_control, TRIMINFO_RELOAD);
 
 	/* Get the compensation parameter */
-	te_temp = readl(&reg->triminfo);
+	te_temp = read32(&reg->triminfo);
 	info->te1 = te_temp & TRIM_INFO_MASK;
 	info->te2 = ((te_temp >> 8) & TRIM_INFO_MASK);
 
@@ -169,8 +169,8 @@ static void tmu_setup_parameters(struct tmu_info *info)
 			(hwtrip_code << 24));
 
 	/* Set interrupt level */
-	writel(rising_value, &reg->threshold_temp_rise);
-	writel(cooling_temp, &reg->threshold_temp_fall);
+	write32(&reg->threshold_temp_rise, rising_value);
+	write32(&reg->threshold_temp_fall, cooling_temp);
 
 	/*
 	 * Need to init all register settings after getting parameter info
@@ -183,20 +183,20 @@ static void tmu_setup_parameters(struct tmu_info *info)
 	 * TODO(bhthompson): rewrite this code such that we are not performing
 	 * a hard wipe of tmu_control and re verify functionality.
 	 */
-	writel(data->slope, &reg->tmu_control);
+	write32(&reg->tmu_control, data->slope);
 
-	writel(INTCLEARALL, &reg->intclear);
+	write32(&reg->intclear, INTCLEARALL);
 	/* TMU core enable */
-	con = readl(&reg->tmu_control);
+	con = read32(&reg->tmu_control);
 	con |= (info->tmu_mux << 20) | THERM_TRIP_EN | CORE_EN;
 
-	writel(con, &reg->tmu_control);
+	write32(&reg->tmu_control, con);
 
 	/* Enable HW thermal trip */
 	power_enable_hw_thermal_trip();
 
 	/* LEV1 LEV2 interrupt enable */
-	writel(INTEN_RISE1 | INTEN_RISE2, &reg->inten);
+	write32(&reg->inten, INTEN_RISE1 | INTEN_RISE2);
 }
 
 /*
diff --git a/src/soc/samsung/exynos5420/trustzone.c b/src/soc/samsung/exynos5420/trustzone.c
index 983690dbef..5712768355 100644
--- a/src/soc/samsung/exynos5420/trustzone.c
+++ b/src/soc/samsung/exynos5420/trustzone.c
@@ -33,10 +33,10 @@ void trustzone_init(void)
 	for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
 		tzpc = (struct exynos_tzpc *)addr;
 		if (addr == TZPC0_BASE)
-			writel(R0SIZE, &tzpc->r0size);
-		writel(DECPROTXSET, &tzpc->decprot0set);
-		writel(DECPROTXSET, &tzpc->decprot1set);
-		writel(DECPROTXSET, &tzpc->decprot2set);
-		writel(DECPROTXSET, &tzpc->decprot3set);
+			write32(&tzpc->r0size, R0SIZE);
+		write32(&tzpc->decprot0set, DECPROTXSET);
+		write32(&tzpc->decprot1set, DECPROTXSET);
+		write32(&tzpc->decprot2set, DECPROTXSET);
+		write32(&tzpc->decprot3set, DECPROTXSET);
 	}
 }
diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c
index 74e5067b0d..bfdd54a891 100644
--- a/src/soc/samsung/exynos5420/uart.c
+++ b/src/soc/samsung/exynos5420/uart.c
@@ -66,7 +66,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
 	uclk = clock_get_periph_rate(PERIPH_ID_UART3);
 	val = uclk / default_baudrate();
 
-	writel(val / 16 - 1, &uart->ubrdiv);
+	write32(&uart->ubrdiv, val / 16 - 1);
 
 	/*
 	 * FIXME(dhendrix): the original uart.h had a "br_rest" value which
@@ -88,12 +88,12 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
 static void exynos5_init_dev(struct s5p_uart *uart)
 {
 	/* enable FIFOs */
-	writel(0x1, &uart->ufcon);
-	writel(0, &uart->umcon);
+	write32(&uart->ufcon, 0x1);
+	write32(&uart->umcon, 0);
 	/* 8N1 */
-	writel(0x3, &uart->ulcon);
+	write32(&uart->ulcon, 0x3);
 	/* No interrupts, no DMA, pure polling */
-	writel(0x245, &uart->ucon);
+	write32(&uart->ucon, 0x245);
 
 	serial_setbrg_dev(uart);
 }
@@ -114,7 +114,7 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
 	else
 		mask = 0xf;
 
-	return readl(&uart->uerstat) & mask;
+	return read32(&uart->uerstat) & mask;
 }
 
 /*
@@ -125,13 +125,13 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
 static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
 {
 	/* wait for character to arrive */
-	while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
+	while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
 					 RX_FIFO_FULL_MASK))) {
 		if (exynos5_uart_err_check(uart, 0))
 			return 0;
 	}
 
-	return readb(&uart->urxh) & 0xff;
+	return read8(&uart->urxh) & 0xff;
 }
 
 /*
@@ -140,12 +140,12 @@ static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
 static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data)
 {
 	/* wait for room in the tx FIFO */
-	while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
+	while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
 		if (exynos5_uart_err_check(uart, 1))
 			return;
 	}
 
-	writeb(data, &uart->utxh);
+	write8(&uart->utxh, data);
 }
 
 uintptr_t uart_platform_base(int idx)
diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c
index 0df63e2666..9313fea147 100644
--- a/src/soc/samsung/exynos5420/usb.c
+++ b/src/soc/samsung/exynos5420/usb.c
@@ -57,23 +57,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
 
 	/* Set relevant registers to default values (clearing all reset bits) */
 
-	writel(0x1 << 24 |	/* activate PHY low power states */
-	       0x4 << 19 |	/* low power delay value */
-	       0x1 << 18 |	/* activate PHY low power delay */
-	       0x1 << 17 |	/* enable SuperSpeed PHY suspend */
-	       0x1 << 1 |	/* default Tx deemphasis value */
-	       0, &dwc3->usb3pipectl);
+	write32(&dwc3->usb3pipectl,
+		0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0);
 
 	/* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */
-	writel(0x9 << 10 |	/* PHY clock turnaround for 8-bit UTMI+ */
-	       0x1 << 8 |	/* enable PHY sleep in L1 */
-	       0x1 << 6 |	/* enable PHY suspend */
-	       0, &dwc3->usb2phycfg);
-
-	writel(0x5dc << 19 |	/* suspend clock scale for 24MHz */
-	       0x1 << 16 |	/* retry SS three times (bugfix from U-Boot) */
-	       0x1 << 12 |	/* port capability HOST */
-	       0, &dwc3->ctl);
+	write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0);
+
+	write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0);
 }
 
 void setup_usb_drd0_dwc3()
@@ -96,44 +86,25 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
 	setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
 
 	/* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
-	writel(1 << 6, &phy->utmi);
-
-	writel(0x88 << 23 |	/* spread spectrum refclk selector */
-	       0x1 << 20 |	/* enable spread spectrum */
-	       0x1 << 19 |	/* enable prescaler refclk */
-	       0x68 << 11 |	/* multiplier for 24MHz refclk */
-	       0x5 << 5 |	/* select 24MHz refclk (weird, from U-Boot) */
-	       0x1 << 4 |	/* power supply in normal operating mode */
-	       0x3 << 2 |	/* use external refclk (undocumented on 5420?)*/
-	       0x1 << 1 |	/* force port reset */
-	       0x1 << 0 |	/* normal operating mode */
-	       0, &phy->clkrst);
-
-	writel(0x9 << 26 |	/* LOS level */
-	       0x3 << 22 |	/* TX VREF tune */
-	       0x1 << 20 |	/* TX rise tune */
-	       0x1 << 18 |	/* TX res tune */
-	       0x3 << 13 |	/* TX HS X Vtune */
-	       0x3 << 9 |	/* TX FS/LS tune */
-	       0x3 << 6 |	/* SQRX tune */
-	       0x4 << 3 |	/* OTG tune */
-	       0x4 << 0 |	/* comp disc tune */
-	       0, &phy->param0);
-
-	writel(0x7f << 19 |	/* reserved */
-	       0x7f << 12 |	/* Tx launch amplitude */
-	       0x20 << 6 |	/* Tx deemphasis 6dB */
-	       0x1c << 0 |	/* Tx deemphasis 3.5dB (value from U-Boot) */
-	       0, &phy->param1);
+	write32(&phy->utmi, 1 << 6);
+
+	write32(&phy->clkrst,
+		0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0);
+
+	write32(&phy->param0,
+		0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0);
+
+	write32(&phy->param1,
+		0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0);
 
 	/* disable all test features */
-	writel(0, &phy->test);
+	write32(&phy->test, 0);
 
 	/* UTMI clock select? ("must be 0x1") */
-	writel(0x1 << 2, &phy->utmiclksel);
+	write32(&phy->utmiclksel, 0x1 << 2);
 
 	/* Samsung magic, undocumented (from U-Boot) */
-	writel(0x0, &phy->resume);
+	write32(&phy->resume, 0x0);
 
 	udelay(10);
 	clrbits_le32(&phy->clkrst, 0x1 << 1);  /* deassert port reset */
@@ -163,7 +134,7 @@ void setup_usb_host_phy(int hsic_gpio)
 	printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
 			hsic_gpio ? "with" : "without");
 
-	hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
+	hostphy_ctrl0 = read32(&exynos_usb_host_phy->usbphyctrl0);
 	hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
 			   HOST_CTRL0_COMMONON_N |
 			   /* HOST Phy setting */
@@ -177,7 +148,7 @@ void setup_usb_host_phy(int hsic_gpio)
 			  /* HOST Phy setting */
 			  HOST_CTRL0_LINKSWRST |
 			  HOST_CTRL0_UTMISWRST);
-	writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
+	write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0);
 	udelay(10);
 	clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
 		     HOST_CTRL0_LINKSWRST |