diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-09 18:55:58 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-10 21:25:53 +0000 |
| commit | 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d (patch) | |
| tree | 7b5096ca1f81fecf70418020aba184e446f995e0 /src/soc/samsung | |
| parent | 1895838e7a3807a6fce324f0dfed193a3821f6df (diff) | |
src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/samsung')
| -rw-r--r-- | src/soc/samsung/exynos5420/include/soc/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/include/soc/setup.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index 1f13bb9e62..bc5d0669da 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -26,7 +26,7 @@ SECTIONS { SRAM_START(0x2020000) /* 17K hole, includes BL1 */ - /* Bootblock is preceeded by 16 byte variable length BL2 checksum. */ + /* Bootblock is preceded by 16 byte variable length BL2 checksum. */ BOOTBLOCK(0x2024410, 32K - 16) /* 15K hole */ ROMSTAGE(0x2030000, 128K) diff --git a/src/soc/samsung/exynos5420/include/soc/setup.h b/src/soc/samsung/exynos5420/include/soc/setup.h index f024a2df45..139f5b756a 100644 --- a/src/soc/samsung/exynos5420/include/soc/setup.h +++ b/src/soc/samsung/exynos5420/include/soc/setup.h @@ -729,7 +729,7 @@ struct exynos5_phy_control; #define CTRL_RDLAT_OFFSET 0 #define CMD_DEFAULT_LPDDR3 0xF -#define CMD_DEFUALT_OFFSET 0 +#define CMD_DEFAULT_OFFSET 0 #define T_WRDATA_EN 0x7 #define T_WRDATA_EN_DDR3 0x8 /* FIXME(dhendrix): 6 for DDR3? see T_wrdata_en */ #define T_WRDATA_EN_OFFSET 16 |