Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

6 files changed, 67 insertions, 67 deletions

diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c
index b578133ea4..fe11cdecff 100644
--- a/src/soc/samsung/exynos5420/clock.c
+++ b/src/soc/samsung/exynos5420/clock.c
@@ -390,7 +390,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor)
 		      periph_id);
 		return;
 	}
-	clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift);
+	clrsetbits32(reg, mask << shift, (divisor & mask) << shift);
 }
 
 void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor)
@@ -425,7 +425,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor)
 		      periph_id);
 		return;
 	}
-	clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift);
+	clrsetbits32(reg, mask << shift, (divisor & mask) << shift);
 }
 
 /**
@@ -607,7 +607,7 @@ int clock_epll_set_rate(unsigned long rate)
 
 void clock_select_i2s_clk_source(void)
 {
-	clrsetbits_le32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK,
+	clrsetbits32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK,
 			(CLK_SRC_SCLK_EPLL));
 }
 
@@ -627,7 +627,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 		printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
 		return -1;
 	}
-	clrsetbits_le32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK,
+	clrsetbits32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK,
 				(div & AUDIO_1_RATIO_MASK));
 	return 0;
 }
diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c
index eae08a8dea..92abf32081 100644
--- a/src/soc/samsung/exynos5420/clock_init.c
+++ b/src/soc/samsung/exynos5420/clock_init.c
@@ -42,7 +42,7 @@ void system_clock_init(void)
 	write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL);
 	write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
 
-	setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
+	setbits32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
 
 	write32(&exynos_clock->clk_src_top6, 0);
 
@@ -52,7 +52,7 @@ void system_clock_init(void)
 	write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL);
 
 	/* switch A15 clock source to OSC clock before changing APLL */
-	clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT);
+	clrbits32(&exynos_clock->clk_src_cpu, APLL_FOUT);
 
 	/* Set APLL */
 	write32(&exynos_clock->apll_con1, APLL_CON1_VAL);
@@ -62,13 +62,13 @@ void system_clock_init(void)
 		;
 
 	/* now it is safe to switch to APLL */
-	setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT);
+	setbits32(&exynos_clock->clk_src_cpu, APLL_FOUT);
 
 	write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL);
 	write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL);
 
 	/* switch A7 clock source to OSC clock before changing KPLL */
-	clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
+	clrbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
 
 	/* Set KPLL*/
 	write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL);
@@ -78,7 +78,7 @@ void system_clock_init(void)
 		;
 
 	/* now it is safe to switch to KPLL */
-	setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
+	setbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
 
 	/* Set MPLL */
 	write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL);
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
index 6ea92ee36f..88dc18d2f6 100644
--- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
@@ -33,10 +33,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	int i, chip;
 
 	/* Enable PAUSE for DREX */
-	setbits_le32(&exynos_clock->pause, ENABLE_BIT);
+	setbits32(&exynos_clock->pause, ENABLE_BIT);
 
 	/* Enable BYPASS mode */
-	setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN);
+	setbits32(&exynos_clock->bpll_con1, BYPASS_EN);
 
 	write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL);
 	do {
@@ -44,7 +44,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		val &= BPLL_SEL_MASK;
 	} while (val != FOUTBPLL);
 
-	clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN);
+	clrbits32(&exynos_clock->bpll_con1, BYPASS_EN);
 
 	/* Specify the DDR memory type as DDR3 */
 	val = read32(&exynos_phy0_control->phy_con0);
@@ -87,8 +87,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control))
 		return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
 
-	clrbits_le32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN);
-	clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN);
+	clrbits32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN);
+	clrbits32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN);
 
 	/* DQ Signal */
 	val = read32(&exynos_phy0_control->phy_con14);
@@ -116,8 +116,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		val = read32(&exynos_drex1->phystatus);
 	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
 
-	clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START);
-	clrbits_le32(&exynos_drex1->concontrol, DFI_INIT_START);
+	clrbits32(&exynos_drex0->concontrol, DFI_INIT_START);
+	clrbits32(&exynos_drex1->concontrol, DFI_INIT_START);
 
 	update_reset_dll(exynos_drex0, mem->mem_type);
 	update_reset_dll(exynos_drex1, mem->mem_type);
@@ -205,8 +205,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL);
 		write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL);
 
-		setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN);
-		setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN);
+		setbits32(&exynos_phy0_control->phy_con0, P0_CMD_EN);
+		setbits32(&exynos_phy1_control->phy_con0, P0_CMD_EN);
 
 		val = PHY_CON2_RESET_VAL;
 		val |= INIT_DESKEW_EN;
@@ -243,11 +243,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 				val | (chip << DIRECT_CMD_CHIP_SHIFT));
 		}
 
-		setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN);
-		setbits_le32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN);
+		setbits32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN);
+		setbits32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN);
 
-		setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE);
-		setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE);
+		setbits32(&exynos_phy0_control->phy_con0, CTRL_SHGATE);
+		setbits32(&exynos_phy1_control->phy_con0, CTRL_SHGATE);
 
 		val = read32(&exynos_phy0_control->phy_con1);
 		val &= ~(CTRL_GATEDURADJ_MASK);
@@ -303,8 +303,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0));
 		write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1));
 
-		setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN);
-		setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN);
+		setbits32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN);
+		setbits32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN);
 	}
 
 	/* Send PALL command */
@@ -332,8 +332,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	 * this saves around 25 mw dmc power as compared to the power
 	 * consumption without these bits enabled
 	 */
-	setbits_le32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG);
-	setbits_le32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG);
+	setbits32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG);
+	setbits32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG);
 
 	return 0;
 }
diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c
index 9dfffd6ee6..b59162eccd 100644
--- a/src/soc/samsung/exynos5420/power.c
+++ b/src/soc/samsung/exynos5420/power.c
@@ -25,7 +25,7 @@
 static void ps_hold_setup(void)
 {
 	/* Set PS-Hold high */
-	setbits_le32(&exynos_power->ps_hold_ctrl,
+	setbits32(&exynos_power->ps_hold_ctrl,
 		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 }
 
@@ -34,13 +34,13 @@ void power_reset(void)
 	/* Clear inform1 so there's no change we think we've got a wake reset */
 	exynos_power->inform1 = 0;
 
-	setbits_le32(&exynos_power->sw_reset, 1);
+	setbits32(&exynos_power->sw_reset, 1);
 }
 
 /* This function never returns */
 void power_shutdown(void)
 {
-	clrbits_le32(&exynos_power->ps_hold_ctrl,
+	clrbits32(&exynos_power->ps_hold_ctrl,
 		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 
 	halt();
@@ -48,13 +48,13 @@ void power_shutdown(void)
 
 void power_enable_dp_phy(void)
 {
-	setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
+	setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
 }
 
 void power_enable_hw_thermal_trip(void)
 {
 	/* Enable HW thermal trip */
-	setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
+	setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
 }
 
 uint32_t power_read_reset_status(void)
@@ -78,7 +78,7 @@ int power_init(void)
 void power_enable_xclkout(void)
 {
 	/* use xxti for xclk out */
-	clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
+	clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
 			PMU_DEBUG_XXTI);
 }
 
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 1903f6b3b9..5637b0215d 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -89,10 +89,10 @@ static void spi_sw_reset(struct exynos_spi *regs, int word)
 	if (swap_cfg != orig_swap_cfg)
 		write32(&regs->swap_cfg, swap_cfg);
 
-	clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
-	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
-	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
-	setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+	clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+	setbits32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits32(&regs->ch_cfg, SPI_CH_RST);
+	setbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
 }
 
 static void exynos_spi_init(struct exynos_spi *regs)
@@ -100,14 +100,14 @@ static void exynos_spi_init(struct exynos_spi *regs)
 	// Set FB_CLK_SEL.
 	write32(&regs->fb_clk, SPI_FB_DELAY_180);
 	// CPOL: Active high.
-	clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L);
+	clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L);
 
 	// Clear rx and tx channel if set priveously.
-	clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+	clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
 
-	setbits_le32(&regs->swap_cfg,
+	setbits32(&regs->swap_cfg,
 		     SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP);
-	clrbits_le32(&regs->ch_cfg, SPI_CH_HS_EN);
+	clrbits32(&regs->ch_cfg, SPI_CH_HS_EN);
 
 	// Do a soft reset, which will also enable both channels.
 	spi_sw_reset(regs, 1);
@@ -117,7 +117,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 {
 	struct exynos_spi *regs = to_exynos_spi(slave)->regs;
 	// TODO(hungte) Add some delay if too many transactions happen at once.
-	clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
+	clrbits32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
 	return 0;
 }
 
@@ -201,7 +201,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_
 static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 {
 	struct exynos_spi *regs = to_exynos_spi(slave)->regs;
-	setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
+	setbits32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);
 }
 
 static int spi_ctrlr_setup(const struct spi_slave *slave)
diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c
index 9dda4c100d..2f141c1b67 100644
--- a/src/soc/samsung/exynos5420/usb.c
+++ b/src/soc/samsung/exynos5420/usb.c
@@ -25,9 +25,9 @@
 
 static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
 {
-	setbits_le32(&dwc3->ctl, 0x1 << 11);		/* core soft reset */
-	setbits_le32(&dwc3->usb3pipectl, 0x1 << 31);	/* PHY soft reset */
-	setbits_le32(&dwc3->usb2phycfg, 0x1 << 31);	/* PHY soft reset */
+	setbits32(&dwc3->ctl, 0x1 << 11);		/* core soft reset */
+	setbits32(&dwc3->usb3pipectl, 0x1 << 31);	/* PHY soft reset */
+	setbits32(&dwc3->usb2phycfg, 0x1 << 31);	/* PHY soft reset */
 }
 
 void reset_usb_drd0_dwc3()
@@ -89,7 +89,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
 	/* Set all PHY registers to default values */
 
 	/* XHCI Version 1.0, Frame Length adjustment 30 MHz */
-	setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
+	setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
 
 	/* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
 	write32(&phy->utmi, 1 << 6);
@@ -132,20 +132,20 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
 	write32(&phy->resume, 0x0);
 
 	udelay(10);
-	clrbits_le32(&phy->clkrst, 0x1 << 1);  /* deassert port reset */
+	clrbits32(&phy->clkrst, 0x1 << 1);  /* deassert port reset */
 }
 
 void setup_usb_drd0_phy()
 {
 	printk(BIOS_DEBUG, "Powering up USB DRD0 PHY\n");
-	setbits_le32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+	setbits32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN);
 	setup_drd_phy(exynos_usb_drd0_phy);
 }
 
 void setup_usb_drd1_phy()
 {
 	printk(BIOS_DEBUG, "Powering up USB DRD1 PHY\n");
-	setbits_le32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+	setbits32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN);
 	setup_drd_phy(exynos_usb_drd1_phy);
 }
 
@@ -153,8 +153,8 @@ void setup_usb_host_phy(int hsic_gpio)
 {
 	unsigned int hostphy_ctrl0;
 
-	setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
-	setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+	setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
+	setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN);
 
 	printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
 			hsic_gpio ? "with" : "without");
@@ -175,17 +175,17 @@ void setup_usb_host_phy(int hsic_gpio)
 			  HOST_CTRL0_UTMISWRST);
 	write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0);
 	udelay(10);
-	clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
-		     HOST_CTRL0_LINKSWRST |
-		     HOST_CTRL0_UTMISWRST);
+	clrbits32(&exynos_usb_host_phy->usbphyctrl0,
+		  HOST_CTRL0_LINKSWRST |
+		  HOST_CTRL0_UTMISWRST);
 	udelay(20);
 
 	/* EHCI Ctrl setting */
-	setbits_le32(&exynos_usb_host_phy->ehcictrl,
-		     EHCICTRL_ENAINCRXALIGN |
-		     EHCICTRL_ENAINCR4 |
-		     EHCICTRL_ENAINCR8 |
-		     EHCICTRL_ENAINCR16);
+	setbits32(&exynos_usb_host_phy->ehcictrl,
+		  EHCICTRL_ENAINCRXALIGN |
+		  EHCICTRL_ENAINCR4 |
+		  EHCICTRL_ENAINCR8 |
+		  EHCICTRL_ENAINCR16);
 
 	/* HSIC USB Hub initialization. */
 	if (hsic_gpio) {
@@ -194,15 +194,15 @@ void setup_usb_host_phy(int hsic_gpio)
 		gpio_direction_output(hsic_gpio, 1);
 		udelay(5000);
 
-		clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
-			     HOST_CTRL0_SIDDQ |
-			     HOST_CTRL0_FORCESLEEP |
-			     HOST_CTRL0_FORCESUSPEND);
-		setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
-			     HOST_CTRL0_PHYSWRST);
+		clrbits32(&exynos_usb_host_phy->hsicphyctrl1,
+			  HOST_CTRL0_SIDDQ |
+			  HOST_CTRL0_FORCESLEEP |
+			  HOST_CTRL0_FORCESUSPEND);
+		setbits32(&exynos_usb_host_phy->hsicphyctrl1,
+			  HOST_CTRL0_PHYSWRST);
 		udelay(10);
-		clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
-			     HOST_CTRL0_PHYSWRST);
+		clrbits32(&exynos_usb_host_phy->hsicphyctrl1,
+			  HOST_CTRL0_PHYSWRST);
 	}
 
 	/* At this point we need to wait for 50ms before talking to