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| author | Hannah Williams <hannah.williams@intel.com> | 2017-06-24 08:33:15 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-28 16:27:53 +0000 |
| commit | a61884a8a1338c0e6128cf050827c5d1cd5ef8f3 (patch) | |
| tree | 6b2279a81a15f8bbbc25ed2a7fc39073264b16e4 /src/soc/samsung/exynos5420 | |
| parent | 3c6377fb4fcdff89e1509e9eeab7ce563dc45053 (diff) | |
soc/intel/apollolake: Add CNVI and PCIE IRQs for GLK
Change-Id: I0387ccf6970e6169cbebd232ae210731338d0900
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/20755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/samsung/exynos5420')
0 files changed, 0 insertions, 0 deletions