diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/samsung/exynos5420/spi.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/samsung/exynos5420/spi.c')
| -rw-r--r-- | src/soc/samsung/exynos5420/spi.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 1903f6b3b9..5637b0215d 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -89,10 +89,10 @@ static void spi_sw_reset(struct exynos_spi *regs, int word) if (swap_cfg != orig_swap_cfg) write32(®s->swap_cfg, swap_cfg); - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); } static void exynos_spi_init(struct exynos_spi *regs) @@ -100,14 +100,14 @@ static void exynos_spi_init(struct exynos_spi *regs) // Set FB_CLK_SEL. write32(®s->fb_clk, SPI_FB_DELAY_180); // CPOL: Active high. - clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); + clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); // Clear rx and tx channel if set priveously. - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->swap_cfg, + setbits32(®s->swap_cfg, SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); - clrbits_le32(®s->ch_cfg, SPI_CH_HS_EN); + clrbits32(®s->ch_cfg, SPI_CH_HS_EN); // Do a soft reset, which will also enable both channels. spi_sw_reset(regs, 1); @@ -117,7 +117,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; // TODO(hungte) Add some delay if too many transactions happen at once. - clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); + clrbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); return 0; } @@ -201,7 +201,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_ static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; - setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); + setbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); } static int spi_ctrlr_setup(const struct spi_slave *slave) |