Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 6 insertions, 6 deletions

diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c
index 9dfffd6ee6..b59162eccd 100644
--- a/src/soc/samsung/exynos5420/power.c
+++ b/src/soc/samsung/exynos5420/power.c
@@ -25,7 +25,7 @@
 static void ps_hold_setup(void)
 {
 	/* Set PS-Hold high */
-	setbits_le32(&exynos_power->ps_hold_ctrl,
+	setbits32(&exynos_power->ps_hold_ctrl,
 		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 }
 
@@ -34,13 +34,13 @@ void power_reset(void)
 	/* Clear inform1 so there's no change we think we've got a wake reset */
 	exynos_power->inform1 = 0;
 
-	setbits_le32(&exynos_power->sw_reset, 1);
+	setbits32(&exynos_power->sw_reset, 1);
 }
 
 /* This function never returns */
 void power_shutdown(void)
 {
-	clrbits_le32(&exynos_power->ps_hold_ctrl,
+	clrbits32(&exynos_power->ps_hold_ctrl,
 		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 
 	halt();
@@ -48,13 +48,13 @@ void power_shutdown(void)
 
 void power_enable_dp_phy(void)
 {
-	setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
+	setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
 }
 
 void power_enable_hw_thermal_trip(void)
 {
 	/* Enable HW thermal trip */
-	setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
+	setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
 }
 
 uint32_t power_read_reset_status(void)
@@ -78,7 +78,7 @@ int power_init(void)
 void power_enable_xclkout(void)
 {
 	/* use xxti for xclk out */
-	clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
+	clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
 			PMU_DEBUG_XXTI);
 }