diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-07 14:59:11 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-08 05:39:07 +0100 |
| commit | 1fc2ba5e6d85f3c7eef00a7e6b0b3ee1352fbfa9 (patch) | |
| tree | c943575806918a817060c0fc638625b42294733e /src/soc/samsung/exynos5420/dmc_init_ddr3.c | |
| parent | de7ed6fc7cdb3f55894e613bdc0c394fa8f57494 (diff) | |
samsung/exynos5420: Spelling Fixes
Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7703
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/soc/samsung/exynos5420/dmc_init_ddr3.c')
| -rw-r--r-- | src/soc/samsung/exynos5420/dmc_init_ddr3.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 4acf7d13f3..28603ae414 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -143,7 +143,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(mem->membaseconfig1, &exynos_tzasc1->membaseconfig1); } - /* Memory Channel Inteleaving Size + /* Memory Channel Interleaving Size * Exynos5420 Channel interleaving = 128 bytes */ /* MEMCONFIG0/1 */ @@ -158,7 +158,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, &exynos_drex1->prechconfig0); - /* TimingRow, TimingData, TimingPower and Timingaref + /* TimingRow, TimingData, TimingPower and Timingref * values as per Memory AC parameters */ writel(mem->timing_ref, &exynos_drex0->timingref); @@ -184,7 +184,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) /* * During Suspend-Resume & S/W-Reset, as soon as PMU releases * pad retention, CKE goes high. This causes memory contents - * not to be retained during DRAM initialization. Therfore, + * not to be retained during DRAM initialization. Therefore, * there is a new control register(0x100431e8[28]) which lets us * release pad retention and retain the memory content until the * initialization is complete. |