diff options
author | Julius Werner <jwerner@chromium.org> | 2015-02-19 20:19:23 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:40 +0200 |
commit | 941847652406982f3c9944fdd98cce4029b533fb (patch) | |
tree | af52ebeaa0245c9a3aa1e25c77f2271b67bff4a8 /src/soc/samsung/exynos5420/dmc_init_ddr3.c | |
parent | 2f37bd65518865688b9234afce0d467508d6f465 (diff) |
arm(64): Manually clean up the mess left by write32() transition
This patch is a manual cleanup of all the rubble left by coccinelle
waltzing through our code base. It's generally not very good with line
breaks and sometimes even eats comments, so this patch is my best
attempt at putting it all back together.
Also finally remove those hated writel()-style macros from the headers.
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d
Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254865
Reviewed-on: http://review.coreboot.org/9837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5420/dmc_init_ddr3.c')
-rw-r--r-- | src/soc/samsung/exynos5420/dmc_init_ddr3.c | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 6972618ac3..5eeb07b016 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -111,10 +111,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) write32(&exynos_drex0->phycontrol0, val); write32(&exynos_drex1->phycontrol0, val); - write32(&exynos_drex0->concontrol, - mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); - write32(&exynos_drex1->concontrol, - mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); + write32(&exynos_drex0->concontrol, mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); + write32(&exynos_drex1->concontrol, mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); do { val = read32(&exynos_drex0->phystatus); @@ -198,9 +200,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) for (i = 0; i < 128; i++) { for (chip = 0; chip < mem->chips_to_configure; chip++) { write32(&exynos_drex0->directcmd, - DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); + DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT)); write32(&exynos_drex1->directcmd, - DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); + DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT)); } } } @@ -324,10 +328,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * read data fetch cycles and enable DREX auto set powerdown * for input buffer of I/O in none read memory state. */ - write32(&exynos_drex0->concontrol, - mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); - write32(&exynos_drex1->concontrol, - mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); + write32(&exynos_drex0->concontrol, mem->concontrol | + (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | + DMC_CONCONTROL_IO_PD_CON(0x2)); + write32(&exynos_drex1->concontrol, mem->concontrol | + (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | + DMC_CONCONTROL_IO_PD_CON(0x2)); /* Enable Clock Gating Control for DMC * this saves around 25 mw dmc power as compared to the power |