arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 11 insertions, 11 deletions

diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c
index c23cfed347..81386b7ec4 100644
--- a/src/soc/samsung/exynos5250/uart.c
+++ b/src/soc/samsung/exynos5250/uart.c
@@ -66,7 +66,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
 	uclk = clock_get_periph_rate(PERIPH_ID_UART3);
 	val = uclk / default_baudrate();
 
-	writel(val / 16 - 1, &uart->ubrdiv);
+	write32(&uart->ubrdiv, val / 16 - 1);
 
 	/*
 	 * FIXME(dhendrix): the original uart.h had a "br_rest" value which
@@ -91,12 +91,12 @@ static void exynos5_init_dev(struct s5p_uart *uart)
 	exynos_pinmux_uart3();
 
 	/* enable FIFOs */
-	writel(0x1, &uart->ufcon);
-	writel(0, &uart->umcon);
+	write32(&uart->ufcon, 0x1);
+	write32(&uart->umcon, 0);
 	/* 8N1 */
-	writel(0x3, &uart->ulcon);
+	write32(&uart->ulcon, 0x3);
 	/* No interrupts, no DMA, pure polling */
-	writel(0x245, &uart->ucon);
+	write32(&uart->ucon, 0x245);
 
 	serial_setbrg_dev(uart);
 }
@@ -117,7 +117,7 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
 	else
 		mask = 0xf;
 
-	return readl(&uart->uerstat) & mask;
+	return read32(&uart->uerstat) & mask;
 }
 
 /*
@@ -128,13 +128,13 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
 static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
 {
 	/* wait for character to arrive */
-	while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
+	while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
 					 RX_FIFO_FULL_MASK))) {
 		if (exynos5_uart_err_check(uart, 0))
 			return 0;
 	}
 
-	return readb(&uart->urxh) & 0xff;
+	return read8(&uart->urxh) & 0xff;
 }
 
 /*
@@ -143,17 +143,17 @@ static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
 static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data)
 {
 	/* wait for room in the tx FIFO */
-	while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
+	while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
 		if (exynos5_uart_err_check(uart, 1))
 			return;
 	}
 
-	writeb(data, &uart->utxh);
+	write8(&uart->utxh, data);
 }
 
 static void exynos5_uart_tx_flush(struct s5p_uart *uart)
 {
-	while (readl(&uart->ufstat) & 0x1ff0000);
+	while (read32(&uart->ufstat) & 0x1ff0000);
 }
 
 uintptr_t uart_platform_base(int idx)