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| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-27 11:30:58 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-03 12:15:22 +0000 |
| commit | 2871e0e78c309041a0f3d6e0d7dca99bcaf9f12a (patch) | |
| tree | d4dfdc04eb5ed56fe0a9c2ce87dc738fbbfafdf7 /src/soc/samsung/exynos5250/timer.c | |
| parent | 95bab4077ee564835a8e2f2f8675c567d5283a86 (diff) | |
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API
Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/samsung/exynos5250/timer.c')
0 files changed, 0 insertions, 0 deletions