diff options
author | Julius Werner <jwerner@chromium.org> | 2015-02-19 14:51:15 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:28 +0200 |
commit | 2f37bd65518865688b9234afce0d467508d6f465 (patch) | |
tree | eba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/samsung/exynos5250/spi.c | |
parent | 1f60f971fc89ef841e81b978964b38278d597b1d (diff) |
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5250/spi.c')
-rw-r--r-- | src/soc/samsung/exynos5250/spi.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index 33a8c740f7..fed3aa7518 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -46,25 +46,25 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, out_bytes = in_bytes = todo; setbits_le32(®s->ch_cfg, SPI_CH_RST); clrbits_le32(®s->ch_cfg, SPI_CH_RST); - writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + write32(®s->pkt_cnt, ((todo * 8) / 32) | SPI_PACKET_CNT_EN); while (in_bytes) { uint32_t spi_sts; int temp; - spi_sts = readl(®s->spi_sts); + spi_sts = read32(®s->spi_sts); rx_lvl = ((spi_sts >> 15) & 0x7f); tx_lvl = ((spi_sts >> 6) & 0x7f); while (tx_lvl < 32 && out_bytes) { // TODO The "writing" (tx) is not supported now; that's // why we write garbage to keep driving FIFO clock. temp = 0xffffffff; - writel(temp, ®s->tx_data); + write32(®s->tx_data, temp); out_bytes -= 4; tx_lvl += 4; } while (rx_lvl >= 4 && in_bytes) { - temp = readl(®s->rx_data); + temp = read32(®s->rx_data); if (rxp) *rxp++ = temp; in_bytes -= 4; @@ -79,9 +79,9 @@ int exynos_spi_open(struct exynos_spi *regs) /* set the spi1 GPIO */ /* set pktcnt and enable it */ - writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + write32(®s->pkt_cnt, 4 | SPI_PACKET_CNT_EN); /* set FB_CLK_SEL */ - writel(SPI_FB_DELAY_180, ®s->fb_clk); + write32(®s->fb_clk, SPI_FB_DELAY_180); /* set CH_WIDTH and BUS_WIDTH as word */ setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); @@ -109,10 +109,10 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ /* Send read instruction (0x3h) followed by a 24 bit addr */ - writel((SF_READ_DATA_CMD << 24) | off, ®s->tx_data); + write32(®s->tx_data, (SF_READ_DATA_CMD << 24) | off); /* waiting for TX done */ - while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)); + while (!(read32(®s->spi_sts) & SPI_ST_TX_DONE)); for (upto = 0, i = 0; upto < len; upto += todo, i++) { todo = MIN(len - upto, (1 << 15)); @@ -132,7 +132,7 @@ int exynos_spi_close(struct exynos_spi *regs) */ clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); - writel(0, ®s->swap_cfg); + write32(®s->swap_cfg, 0); /* * Flush spi tx, rx fifos and reset the SPI controller |