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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 22:09:08 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-07-09 21:28:25 +0000
commit5532d93990fbb1d780224d5a971412e19c18fb1b (patch)
treefa29ad21bf611c11ecf2c00ea3fc98f091759c34 /src/soc/samsung/exynos5250/dmc_init_ddr3.c
parent4a1938f186091ea69fb8dcf480477eb5259573da (diff)
soc/samsung/exynos5250: Drop dead code
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I4772680875b20308e57da073bbcdc4597aeed893 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43215 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5250/dmc_init_ddr3.c')
-rw-r--r--src/soc/samsung/exynos5250/dmc_init_ddr3.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
index 029171efdc..f4150203ea 100644
--- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
@@ -19,20 +19,6 @@ static void reset_phy_ctrl(void)
write32(&exynos_clock->lpddr3phy_ctrl,
LPDDR3PHY_CTRL_PHY_RESET_DISABLE);
-#if 0
- /*
- * For proper memory initialization there should be a minimum delay of
- * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal.
- * The below value is an approximate value whose calculation in done
- * considering that sdelay takes 2 instruction for every 1 delay cycle.
- * And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec
- * So for 500 usec, the number of delay cycle should be
- * (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000
- *
- * TODO(hatim.rv@samsung.com): Implement the delay using timer/counter
- */
- sdelay(425000);
-#endif
udelay(500);
}