New mechanism to define SRAM/memory map with automatic bounds checking

This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>

1 files changed, 14 insertions, 14 deletions

diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c
index 10b33f0c2b..e46221cd2d 100644
--- a/src/soc/samsung/exynos5250/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5250/alternate_cbfs.c
@@ -22,6 +22,7 @@
 #include <cbfs.h>  /* This driver serves as a CBFS media source. */
 #include <stdlib.h>
 #include <string.h>
+#include <symbols.h>
 #include <console/console.h>
 #include "alternate_cbfs.h"
 #include "power.h"
@@ -33,14 +34,14 @@
  * by the IROM / BL1, so this code has nothing to do with them.
  *
  * The third transfer is a valid CBFS image that contains only the romstage,
- * and must be small enough to fit into alternate_cbfs_size[__BOOT_BLOCK__] in
+ * and must be small enough to fit into the PRE_RAM CBFS cache in
  * IRAM. It is loaded when this function gets called in the boot block, and
  * the normal CBFS code extracts the romstage from it.
  *
  * The fourth transfer is also a CBFS image, but can be of arbitrary size and
  * should contain all available stages/payloads/etc. It is loaded when this
  * function is called a second time at the end of the romstage, and copied to
- * alternate_cbfs_buffer[!__BOOT_BLOCK__] in DRAM. It will reside there for the
+ * the romstage/ramstage CBFS cache in DRAM. It will reside there for the
  * rest of the firmware's lifetime and all subsequent stages (which will not
  * have __PRE_RAM__ defined) can just directly reference it there.
  */
@@ -60,12 +61,12 @@ static int usb_cbfs_open(struct cbfs_media *media)
 
 	/*
 	 * We need to trust the host/irom to copy the image to our
-	 * alternate_cbfs_buffer address... there is no way to control or even
+	 * _cbfs_cache address... there is no way to control or even
 	 * check the transfer size or target address from our side.
 	 */
 
 	printk(BIOS_DEBUG, "USB A-A transfer successful, CBFS image should now"
-		" be at %p\n", alternate_cbfs_buffer);
+		" be at %p\n", _cbfs_cache);
 	first_run = 0;
 #endif
 	return 0;
@@ -86,11 +87,11 @@ static int sdmmc_cbfs_open(struct cbfs_media *media)
 	 * In the bootblock, we just copy the small part that fits in the buffer
 	 * and hope that it's enough (since the romstage is currently always the
 	 * first component in the image, this should work out). In the romstage,
-	 * we copy until our buffer is full (currently 12M) to avoid the pain of
+	 * we copy until our cache is full (currently 12M) to avoid the pain of
 	 * figuring out the true image size from in here. Since this is mainly a
 	 * developer/debug boot mode, those shortcomings should be bearable.
 	 */
-	const u32 count = alternate_cbfs_size / 512;
+	const u32 count = _cbfs_cache_size / 512;
 	static int first_run = 1;
 	int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
 		*irom_sdmmc_read_blocks_ptr;
@@ -98,13 +99,13 @@ static int sdmmc_cbfs_open(struct cbfs_media *media)
 	if (!first_run)
 		return 0;
 
-	if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) {
+	if (!irom_load_sdmmc(1, count, _cbfs_cache)) {
 		printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
 		return -1;
 	}
 
 	printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
-		" at %p\n", alternate_cbfs_buffer);
+		" at %p\n", _cbfs_cache);
 	first_run = 0;
 #endif
 	return 0;
@@ -115,16 +116,16 @@ static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
 static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
 				  size_t offset, size_t count)
 {
-	ASSERT(offset + count < alternate_cbfs_size);
-	memcpy(dest, alternate_cbfs_buffer + offset, count);
+	ASSERT(offset + count < _cbfs_cache_size);
+	memcpy(dest, _cbfs_cache + offset, count);
 	return count;
 }
 
 static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
 				   size_t count)
 {
-	ASSERT(offset + count < alternate_cbfs_size);
-	return alternate_cbfs_buffer + offset;
+	ASSERT(offset + count < _cbfs_cache_size);
+	return _cbfs_cache + offset;
 }
 
 static void *alternate_cbfs_unmap(struct cbfs_media *media,
@@ -166,8 +167,7 @@ int init_default_cbfs_media(struct cbfs_media *media)
 		return initialize_exynos_sdmmc_cbfs_media(media);
 	case OM_STAT_SPI:
 		return initialize_exynos_spi_cbfs_media(media,
-			(void*)CONFIG_CBFS_CACHE_ADDRESS,
-			CONFIG_CBFS_CACHE_SIZE);
+			_cbfs_cache, _cbfs_cache_size);
 	default:
 		printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
 			exynos_power->om_stat);