src/soc/samsung: Move common headers to "common/include/soc"

Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

9 files changed, 506 insertions, 0 deletions

diff --git a/src/soc/samsung/common/include/soc/alternate_cbfs.h b/src/soc/samsung/common/include/soc/alternate_cbfs.h
new file mode 100644
index 0000000000..63edc6a902
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/alternate_cbfs.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H
+
+/* These are pointers to function pointers. Double indirection! */
+static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030;
+static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044;
+static void **const irom_msh_end_boot_op_emmc_ptr = (void **)0x02020048;
+static void **const irom_spi_sf_read_ptr = (void **)0x02020058;
+static void **const irom_load_image_from_usb_ptr = (void **)0x02020070;
+
+#define SECONDARY_BASE_BOOT_USB 0xfeed0002
+static u32 *const iram_secondary_base = (u32 *)0x02020018;
+
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC  0x8
+#define OM_STAT_SPI  0x14
+#define OM_STAT_MASK 0x7f
+
+#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H */
diff --git a/src/soc/samsung/common/include/soc/dsim.h b/src/soc/samsung/common/include/soc/dsim.h
new file mode 100644
index 0000000000..541c72a3c0
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/dsim.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Register map for Exynos5 MIPI-DSIM */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H
+
+/* DSIM register map */
+struct exynos5_dsim {
+	unsigned int status;
+	unsigned int swrst;
+	unsigned int clkctrl;
+	unsigned int timeout;
+	unsigned int config;
+	unsigned int escmode;
+	unsigned int mdresol;
+	unsigned int mvporch;
+	unsigned int mhporch;
+	unsigned int msync;
+	unsigned int sdresol;
+	unsigned int intsrc;
+	unsigned int intmsk;
+	unsigned int pkthdr;
+	unsigned int payload;
+	unsigned int rxfifo;
+	unsigned int res1;
+	unsigned int fifoctrl;
+	unsigned int res2;
+	unsigned int pllctrl;
+	unsigned int plltmr;
+	unsigned int phyacchr;
+	unsigned int phyacchr1;
+};
+check_member(exynos5_dsim, phyacchr1, 0x54);
+
+#define ENABLE		1
+#define DISABLE		0
+
+#define DSIM_SWRST			(1 << 0)
+#define NUM_OF_DAT_LANE_IS_FOUR		(3 << 5)
+#define DATA_LANE_0_EN			(1 << 0)
+#define DATA_LANE_1_EN			(1 << 1)
+#define DATA_LANE_2_EN			(1 << 2)
+#define DATA_LANE_3_EN			(1 << 3)
+#define CLK_LANE_EN			(1 << 4)
+#define ENABLE_ALL_DATA_LANE		DATA_LANE_0_EN | \
+					DATA_LANE_1_EN | \
+					DATA_LANE_2_EN | \
+					DATA_LANE_3_EN
+#define	MAIN_PIX_FORMAT_OFFSET		12
+#define RGB_565_16_BIT			0x4
+#define VIDEO_MODE			(1 << 25)
+#define BURST_MODE			(1 << 26)
+
+#define DSIM_PHYACCHR_AFC_EN		(1 << 14)
+#define DSIM_PHYACCHR_AFC_CTL_OFFSET	5
+
+#define DSIM_PLLCTRL_PMS_OFFSET		1
+#define DSIM_FREQ_BAND_OFFSET		24
+
+#define LANE_ESC_CLK_EN_ALL		(0x1f << 19)
+#define BYTE_CLK_EN			(1 << 24)
+#define DSIM_ESC_CLK_EN			(1 << 28)
+#define TXREQUEST_HS_CLK_ON		(1 << 31)
+
+#define LP_MODE_ENABLE			(1 << 7)
+#define STOP_STATE_CNT_OFFSET		21
+
+#define MAIN_VBP_OFFSET		0
+#define STABLE_VFP_OFFSET	16
+#define CMD_ALLOW_OFFSET	28
+
+#define MAIN_HBP_OFFSET		0
+#define MAIN_HFP_OFFSET		16
+
+#define MAIN_HSA_OFFSET		0
+#define MAIN_VSA_OFFSET		22
+
+#define MAIN_STANDBY		(1 << 31)
+#define MAIN_VRESOL_OFFSET	16
+#define MAIN_HRESOL_OFFSET	0
+
+#define SFR_FIFO_EMPTY		(1 << 29)
+
+#define DSIM_PLL_EN_SHIFT	(1 << 23)
+#define PLL_STABLE		(1 << 31)
+
+#define DSIM_STOP_STATE_DAT(x)  (((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK     (1 << 8)
+#define DSIM_TX_READY_HS_CLK    (1 << 10)
+
+#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H */
diff --git a/src/soc/samsung/common/include/soc/i2c.h b/src/soc/samsung/common/include/soc/i2c.h
new file mode 100644
index 0000000000..44feb6b046
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/i2c.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H
+
+void i2c_init(unsigned int bus, int speed, int slaveadd);
+
+#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H */
diff --git a/src/soc/samsung/common/include/soc/i2s-regs.h b/src/soc/samsung/common/include/soc/i2s-regs.h
new file mode 100644
index 0000000000..012ca693bb
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/i2s-regs.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Taken from the kernel code */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H
+
+#define I2SCON		0x0
+#define I2SMOD		0x4
+#define I2SFIC		0x8
+#define I2SPSR		0xc
+#define I2STXD		0x10
+#define I2SRXD		0x14
+#define I2SFICS		0x18
+#define I2STXDS		0x1c
+#define I2SAHB		0x20
+#define I2SSTR0		0x24
+#define I2SSIZE		0x28
+#define I2STRNCNT	0x2c
+#define I2SLVL0ADDR	0x30
+#define I2SLVL1ADDR	0x34
+#define I2SLVL2ADDR	0x38
+#define I2SLVL3ADDR	0x3c
+
+#define CON_RSTCLR		(1 << 31)
+#define CON_FRXOFSTATUS		(1 << 26)
+#define CON_FRXORINTEN		(1 << 25)
+#define CON_FTXSURSTAT		(1 << 24)
+#define CON_FTXSURINTEN		(1 << 23)
+#define CON_TXSDMA_PAUSE	(1 << 20)
+#define CON_TXSDMA_ACTIVE	(1 << 18)
+
+#define CON_FTXURSTATUS		(1 << 17)
+#define CON_FTXURINTEN		(1 << 16)
+#define CON_TXFIFO2_EMPTY	(1 << 15)
+#define CON_TXFIFO1_EMPTY	(1 << 14)
+#define CON_TXFIFO2_FULL	(1 << 13)
+#define CON_TXFIFO1_FULL	(1 << 12)
+
+#define CON_LRINDEX		(1 << 11)
+#define CON_TXFIFO_EMPTY	(1 << 10)
+#define CON_RXFIFO_EMPTY	(1 << 9)
+#define CON_TXFIFO_FULL		(1 << 8)
+#define CON_RXFIFO_FULL		(1 << 7)
+#define CON_TXDMA_PAUSE		(1 << 6)
+#define CON_RXDMA_PAUSE		(1 << 5)
+#define CON_TXCH_PAUSE		(1 << 4)
+#define CON_RXCH_PAUSE		(1 << 3)
+#define CON_TXDMA_ACTIVE	(1 << 2)
+#define CON_RXDMA_ACTIVE	(1 << 1)
+#define CON_ACTIVE		(1 << 0)
+
+#define MOD_OPCLK_CDCLK_OUT	(0 << 30)
+#define MOD_OPCLK_CDCLK_IN	(1 << 30)
+#define MOD_OPCLK_BCLK_OUT	(2 << 30)
+#define MOD_OPCLK_PCLK		(3 << 30)
+#define MOD_OPCLK_MASK		(3 << 30)
+#define MOD_TXS_IDMA		(1 << 28) /* Sec_TXFIFO use I-DMA */
+
+#define MOD_BLCS_SHIFT		26
+#define MOD_BLCS_16BIT		(0 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_8BIT		(1 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_24BIT		(2 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_MASK		(3 << MOD_BLCS_SHIFT)
+
+#define MOD_BLCP_SHIFT		24
+#define MOD_BLCP_16BIT		(0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT		(1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT		(2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK		(3 << MOD_BLCP_SHIFT)
+
+#define MOD_C2DD_HHALF		(1 << 21) /* Discard Higher-half */
+#define MOD_C2DD_LHALF		(1 << 20) /* Discard Lower-half */
+#define MOD_C1DD_HHALF		(1 << 19)
+#define MOD_C1DD_LHALF		(1 << 18)
+#define MOD_DC2_EN		(1 << 17)
+#define MOD_DC1_EN		(1 << 16)
+#define MOD_BLC_16BIT		(0 << 13)
+#define MOD_BLC_8BIT		(1 << 13)
+#define MOD_BLC_24BIT		(2 << 13)
+#define MOD_BLC_MASK		(3 << 13)
+
+#define MOD_IMS_SYSMUX		(1 << 10)
+#define MOD_SLAVE		(1 << 11)
+#define MOD_TXONLY		(0 << 8)
+#define MOD_RXONLY		(1 << 8)
+#define MOD_TXRX		(2 << 8)
+#define MOD_MASK		(3 << 8)
+#define MOD_LR_LLOW		(0 << 7)
+#define MOD_LR_RLOW		(1 << 7)
+#define MOD_SDF_IIS		(0 << 5)
+#define MOD_SDF_MSB		(1 << 5)
+#define MOD_SDF_LSB		(2 << 5)
+#define MOD_SDF_MASK		(3 << 5)
+#define MOD_RCLK_256FS		(0 << 3)
+#define MOD_RCLK_512FS		(1 << 3)
+#define MOD_RCLK_384FS		(2 << 3)
+#define MOD_RCLK_768FS		(3 << 3)
+#define MOD_RCLK_MASK		(3 << 3)
+#define MOD_BCLK_32FS		(0 << 1)
+#define MOD_BCLK_48FS		(1 << 1)
+#define MOD_BCLK_16FS		(2 << 1)
+#define MOD_BCLK_24FS		(3 << 1)
+#define MOD_BCLK_MASK		(3 << 1)
+#define MOD_8BIT		(1 << 0)
+
+#define MOD_CDCLKCON		(1 << 12)
+
+#define PSR_PSREN		(1 << 15)
+
+#define FIC_TXFLUSH		(1 << 15)
+#define FIC_RXFLUSH		(1 << 7)
+
+#define AHB_INTENLVL0		(1 << 24)
+#define AHB_LVL0INT		(1 << 20)
+#define AHB_CLRLVL0INT		(1 << 16)
+#define AHB_DMARLD		(1 << 5)
+#define AHB_INTMASK		(1 << 3)
+#define AHB_DMAEN		(1 << 0)
+#define AHB_LVLINTMASK		(0xf << 20)
+
+#define I2SSIZE_TRNMSK		(0xffff)
+#define I2SSIZE_SHIFT		(16)
+
+#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H */
diff --git a/src/soc/samsung/common/include/soc/sysreg.h b/src/soc/samsung/common/include/soc/sysreg.h
new file mode 100644
index 0000000000..501d6d5af4
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/sysreg.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Register map for Exynos5 sysreg */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H
+
+#include <soc/cpu.h>
+
+/* sysreg map */
+struct exynos5_sysreg {
+	/* Add registers as and when required */
+	unsigned char	res1[0x214];
+	unsigned int	disp1blk_cfg;
+	unsigned char	res2[0x18];
+	unsigned int	usb20_phy_cfg;
+};
+check_member(exynos5_sysreg, usb20_phy_cfg, 0x230);
+
+static struct exynos5_sysreg * const exynos_sysreg =
+		(void *)EXYNOS5_SYSREG_BASE;
+
+#define FIMDBYPASS_DISP1	(1 << 15)
+#define USB20_PHY_CFG_EN	(1 << 0)
+
+#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H */
diff --git a/src/soc/samsung/common/include/soc/tmu.h b/src/soc/samsung/common/include/soc/tmu.h
new file mode 100644
index 0000000000..44996f6fdf
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/tmu.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* EXYNOS - Thermal Management Unit */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H
+
+struct tmu_reg {
+	unsigned int triminfo;
+	unsigned int rsvd1;
+	unsigned int rsvd2;
+	unsigned int rsvd3;
+	unsigned int rsvd4;
+	unsigned int triminfo_control;
+	unsigned int rsvd5;
+	unsigned int rsvd6;
+	unsigned int tmu_control;
+	unsigned int rsvd7;
+	unsigned int tmu_status;
+	unsigned int sampling_internal;
+	unsigned int counter_value0;
+	unsigned int counter_value1;
+	unsigned int rsvd8;
+	unsigned int rsvd9;
+	unsigned int current_temp;
+	unsigned int rsvd10;
+	unsigned int rsvd11;
+	unsigned int rsvd12;
+	unsigned int threshold_temp_rise;
+	unsigned int threshold_temp_fall;
+	unsigned int rsvd13;
+	unsigned int rsvd14;
+	unsigned int past_temp3_0;
+	unsigned int past_temp7_4;
+	unsigned int past_temp11_8;
+	unsigned int past_temp15_12;
+	unsigned int inten;
+	unsigned int intstat;
+	unsigned int intclear;
+	unsigned int rsvd15;
+	unsigned int emul_con;
+};
+check_member(tmu_reg, emul_con, 0x80);
+
+enum tmu_status_t {
+	TMU_STATUS_INIT = 0,
+	TMU_STATUS_NORMAL,
+	TMU_STATUS_WARNING,
+	TMU_STATUS_TRIPPED,
+};
+
+/* Temperature threshold values for various thermal events */
+struct temperature_params {
+	/* minimum value in temperature code range */
+	unsigned int min_val;
+	/* maximum value in temperature code range */
+	unsigned int max_val;
+	/* temperature threshold to start warning */
+	unsigned int start_warning;
+	/* temperature threshold CPU tripping */
+	unsigned int start_tripping;
+	/* temperature threshold for HW tripping */
+	unsigned int hardware_tripping;
+};
+
+/* Pre-defined values and thresholds for calibration of current temperature */
+struct tmu_data {
+	/* pre-defined temperature thresholds */
+	struct temperature_params ts;
+	/* pre-defined efuse range minimum value */
+	unsigned int efuse_min_value;
+	/* pre-defined efuse value for temperature calibration */
+	unsigned int efuse_value;
+	/* pre-defined efuse range maximum value */
+	unsigned int efuse_max_value;
+	/* current temperature sensing slope */
+	unsigned int slope;
+};
+
+/* TMU device specific details and status */
+struct tmu_info {
+	/* base Address for the TMU */
+	unsigned int tmu_base;
+	/* mux Address for the TMU */
+	int tmu_mux;
+	/* pre-defined values for calibration and thresholds */
+	struct tmu_data data;
+	/* value required for triminfo_25 calibration */
+	unsigned int te1;
+	/* value required for triminfo_85 calibration */
+	unsigned int te2;
+	/* TMU DC value for threshold calculation */
+	int dc_value;
+	/* enum value indicating status of the TMU */
+	int tmu_state;
+};
+
+extern struct tmu_info *tmu_info;
+
+/*
+ * Monitors status of the TMU device and exynos temperature
+ *
+ * @info	pointer to TMU info struct
+ * @temp	pointer to the current temperature value
+ * @return	enum tmu_status_t value, code indicating event to execute
+ *		and -1 on error
+ */
+enum tmu_status_t tmu_monitor(struct tmu_info *info, int *temp);
+
+/*
+ * Initialize TMU device
+ *
+ * @info	pointer to TMU info struct
+ * @return	int value, 0 for success
+ */
+int tmu_init(struct tmu_info *info);
+
+#endif	/* SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H */
diff --git a/src/soc/samsung/common/include/soc/trustzone.h b/src/soc/samsung/common/include/soc/trustzone.h
new file mode 100644
index 0000000000..c95e98db16
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/trustzone.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H
+
+#include <stdint.h>
+
+/* Distance between each Trust Zone PC register set */
+#define TZPC_BASE_OFFSET		0x10000
+/* TZPC : Register Offsets */
+#define TZPC0_BASE		0x10100000
+#define TZPC1_BASE		0x10110000
+#define TZPC2_BASE		0x10120000
+#define TZPC3_BASE		0x10130000
+#define TZPC4_BASE		0x10140000
+#define TZPC5_BASE		0x10150000
+#define TZPC6_BASE		0x10160000
+#define TZPC7_BASE		0x10170000
+#define TZPC8_BASE		0x10180000
+#define TZPC9_BASE		0x10190000
+#define TZPC10_BASE		0x100E0000
+#define TZPC11_BASE		0x100F0000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+
+struct exynos_tzpc {
+	u32 r0size;
+	u8 res1[0x7FC];
+	u32 decprot0stat;
+	u32 decprot0set;
+	u32 decprot0clr;
+	u32 decprot1stat;
+	u32 decprot1set;
+	u32 decprot1clr;
+	u32 decprot2stat;
+	u32 decprot2set;
+	u32 decprot2clr;
+	u32 decprot3stat;
+	u32 decprot3set;
+	u32 decprot3clr;
+	u8 res2[0x7B0];
+	u32 periphid0;
+	u32 periphid1;
+	u32 periphid2;
+	u32 periphid3;
+	u32 pcellid0;
+	u32 pcellid1;
+	u32 pcellid2;
+	u32 pcellid3;
+};
+check_member(exynos_tzpc, pcellid3, 0xffc);
+
+void trustzone_init(void);
+
+#endif	/* SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H */
diff --git a/src/soc/samsung/common/include/soc/uart.h b/src/soc/samsung/common/include/soc/uart.h
new file mode 100644
index 0000000000..b530e075e5
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/uart.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H
+
+struct s5p_uart {
+	unsigned int	ulcon;
+	unsigned int	ucon;
+	unsigned int	ufcon;
+	unsigned int	umcon;
+	unsigned int	utrstat;
+	unsigned int	uerstat;
+	unsigned int	ufstat;
+	unsigned int	umstat;
+	unsigned char	utxh;
+	unsigned char	res1[3];
+	unsigned char	urxh;
+	unsigned char	res2[3];
+	unsigned int	ubrdiv;
+	unsigned char	res3[0xffd0];
+};
+check_member(s5p_uart, ubrdiv, 0x28);
+
+#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H */
diff --git a/src/soc/samsung/common/include/soc/wakeup.h b/src/soc/samsung/common/include/soc/wakeup.h
new file mode 100644
index 0000000000..bc678004d0
--- /dev/null
+++ b/src/soc/samsung/common/include/soc/wakeup.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H
+#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP	0x00000BAD
+#define S5P_CHECK_DIDLE	0xBAD00000
+#define S5P_CHECK_LPA	0xABAD0000
+
+enum {
+	// A normal boot (not suspend/resume)
+	IS_NOT_WAKEUP,
+	// A wake up event that can be resumed any time
+	WAKEUP_DIRECT,
+	// A wake up event that must be resumed only after
+	// clock and memory controllers are re-initialized
+	WAKEUP_NEED_CLOCK_RESET,
+};
+
+int wakeup_need_reset(void);
+int get_wakeup_state(void);
+void wakeup(void);
+void wakeup_enable_uart(void);
+
+#endif	/* SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H */