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authorCliff Huang <cliff.huang@intel.com>2023-02-04 21:20:08 -0800
committerFelix Held <felix-coreboot@felixheld.de>2023-02-16 14:12:07 +0000
commit053996283598649d66817a0f7d47a856834962d5 (patch)
tree54575761baa81b6365d3353e1fe5a5ff17ac5c2b /src/soc/rockchip
parent3c31173c1c7c726438824e4e457042c14f815d21 (diff)
soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
_ON() calls _STA() at the beginning. If _STA() indicates the device is ON, it exits immediately. The solution is to move this _STA() check into the ONSK logic. In general cases, ONSK remains '0'. NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following by a device reset such as WWAN device. When such device calls its _RST(), it increments OFSK. When the following _OFF() is called, it was scheduled to skip, it will also increments ONSK. Similarly, when the following _ON() is called, it checks if the previous _OFF was skipped or not. If skipped, it needs to do the same. In normal suspend/resume cases, these two variables remains '0'. No _OFF() and _ON() calls are skipped. entire generated code: Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { Return (One) } Acquire (\_SB.PCI0.R3MX, 0xFFFF) EMPG = Zero Local7 = 0x06 While ((Local7 > Zero)) { If ((AMPG == Zero)) { Break } Sleep (0x10) Local7-- } Release (\_SB.PCI0.R3MX) \_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020, 0x00000020, 0x00000020) \_SB.PCI0.STXS (0x015E) If ((NCB7 == One)) { L23R = One Local7 = 0x14 While ((Local7 > Zero)) { If ((L23R == Zero)) { Break } Sleep (0x10) Local7-- } NCB7 = Zero Local7 = 0x08 While ((Local7 > Zero)) { If ((LASX == One)) { Break } Sleep (0x10) Local7-- } } } Else { ONSK-- } } BUG=b:249931687 BUG=b:241850118 TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72826 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/rockchip')
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