summaryrefslogtreecommitdiff
path: root/src/soc/rockchip
diff options
context:
space:
mode:
authorLucas Chen <lucas.chen@quanta.corp-partner.google.com>2020-10-30 14:11:26 +0800
committerFelix Held <felix-coreboot@felixheld.de>2020-11-06 19:23:04 +0000
commitd8c189b669a8b98448f287fa0872d440b8892dd1 (patch)
tree795cf8de0d44901d7823628f29563d450c97d6dd /src/soc/rockchip
parentea4db9b8fb2e29a1640afbf8b59b974d61c5b6a4 (diff)
zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board
Adjust USB2 phy si setting fine tune on DVT for Ezkinil. BRANCH=zork BUG=b:156315391 TEST=Measuring scope timing and test usb detection Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions