diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-10-02 17:28:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-12-02 22:12:10 +0000 |
| commit | baf27dbaeb1f6791ebfc416f2175507686bd88ac (patch) | |
| tree | 55c9d8224cde44d732b183624abf76b7446e418e /src/soc/rockchip | |
| parent | 4a1cbdd51aafa671ecb6c93a475ca9bf6f9ca914 (diff) | |
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3288/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/memlayout.ld | 9 |
2 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3dc9a9b554..a51df2a9ae 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -17,6 +17,7 @@ config SOC_ROCKCHIP_RK3288 select HAVE_LINEAR_FRAMEBUFFER select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE if SOC_ROCKCHIP_RK3288 diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld index 72836b5130..aa925a25c9 100644 --- a/src/soc/rockchip/rk3399/memlayout.ld +++ b/src/soc/rockchip/rk3399/memlayout.ld @@ -24,11 +24,12 @@ SECTIONS FMAP_CACHE(0xFF8C1400, 2K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4) + BOOTBLOCK(0xFF8D7000, 40K) #endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) + CBFS_MCACHE(0xFF8E1000, 8K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 20K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) SRAM_END(0xFF8F0000) |