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author | Furquan Shaikh <furquan@google.com> | 2019-04-29 14:09:17 -0700 |
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committer | Furquan Shaikh <furquan@google.com> | 2019-05-01 02:18:31 +0000 |
commit | 4c8726574cb36fe0e836bc32fbd453f8770a2ff0 (patch) | |
tree | 6a873d1f5c1ba5c25149ccc72d9367eea0622d1e /src/soc/rockchip | |
parent | 517eda5ca48014ae53315f3afa731be7f39a20f6 (diff) |
soc/intel/common: Set RX_DISABLE for pads configured as NC
For GPIO pads that are configured as no-connect (PAD_NC), setting it
as GPI (with Rx enabled) leads to GPE0_STS being set
incorrectly. Though this is not an issue in practice (GPE0_EN is not
set, so no events triggered), it can confuse users when debugging GPE
related issues.
This change configures PAD_NC to have Rx disabled along with Tx to
ensure that it does not end up setting GPE0_STS bits for unwanted
GPIO pads.
P.S.: IOSSTATE config does not have a TxDRxD setting, so leaving that
configuration as is.
BUG=b:129235068
TEST=Verified that GPE0_STS bits are not set for pads that are marked
as PAD_NC.
Change-Id: I726cc7b86a94e7449352cd8a8806d4d775c593dc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions