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authorMeera Ravindranath <meera.ravindranath@intel.com>2020-02-13 22:07:00 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-02-15 04:10:46 +0000
commit0e61a53b06bf0f1f0eba7a85e0a19fec97375717 (patch)
treea6f05be9364b2944eedee7a256cde7b221f4b63b /src/soc/rockchip
parent77eaecf06b238157decfe19fea02eadfa71a9436 (diff)
soc/tigerlake: Update xhci ACPI files for JSP
ACPI files for xhci in JSL is different from TGL. Hence, renaming xhci.asl to xhci_tgl.asl and adding a new file xhci_jsl.asl for JSL. Also, allowing xhci.asl to choose the correct file based on the SoC selected. BUG=None BRANCH=None TEST=Compilation for JasperLake board is working Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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