diff options
| author | Matt Papageorge <matthewpapa07@gmail.com> | 2020-06-26 08:47:00 -0500 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-24 22:01:51 +0000 |
| commit | ab83b43b34d729ad260d8f68b725ed025eaafb5e (patch) | |
| tree | 7c07485cc1d6bb1b264539d1e32e2786c21650a6 /src/soc/rockchip | |
| parent | 9857c906854752848cbe0b68fb0c35e924a3dd28 (diff) | |
soc/amd/picasso/sb: Gate FCH AL2AHB clocks
Gate the A-Link to AHB Bridge clocks to save power. These
are internal clocks and are unneeded for Raven/Picasso.
This was previously performed within the AGESA FSP but this
change relocates it into coreboot.
BUG=b:154144239
TEST=Check AL2AHB clock gate bits at the end of POST before and
after change with HDT.
Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions